Also assign wr_usedw_32b = dp_fifo_fill_rd_usedw_32b for clarity.

applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd

@@ -831,6 +831,7 @@ BEGIN
     reg_miso     => reg_dp_fifo_monitor_miso,
 
     rd_usedw_32b => dp_fifo_fill_rd_usedw_32b,
+    wr_usedw_32b => dp_fifo_fill_rd_usedw_32b,  -- dp_clk single clock domain for u_dp_fifo_fill, so wr side usedw = rd side usedw
     rd_emp       => dp_fifo_fill_rd_emp,       
     wr_full      => dp_fifo_fill_wr_full,      
     rd_fill_32b  => dp_fifo_fill_rd_fill_32b