From 5f0a79762274ef4e64d75e896f27ae4ceae3c5af Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 1 Aug 2017 11:51:05 +0000
Subject: [PATCH] Also assign wr_usedw_32b = dp_fifo_fill_rd_usedw_32b for
clarity.
---
.../src/vhdl/apertif_unb1_fn_beamformer.vhd | 1 +
1 file changed, 1 insertion(+)
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index 5a56d391bc..ffb3c1e8e8 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -831,6 +831,7 @@ BEGIN
reg_miso => reg_dp_fifo_monitor_miso,
rd_usedw_32b => dp_fifo_fill_rd_usedw_32b,
+ wr_usedw_32b => dp_fifo_fill_rd_usedw_32b, -- dp_clk single clock domain for u_dp_fifo_fill, so wr side usedw = rd side usedw
rd_emp => dp_fifo_fill_rd_emp,
wr_full => dp_fifo_fill_wr_full,
rd_fill_32b => dp_fifo_fill_rd_fill_32b
--
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