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Commit ce1cb44f authored by Eric Kooistra's avatar Eric Kooistra
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Improved stable monitor for out_status(4), added out_status(3) and increased... 

Improved stable monitor for out_status(4), added out_status(3) and increased c_wb_sync_roundtrip_nax by 1.
parent df157fc9
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libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
+ 49
− 8
View file @ ce1cb44f
......@@ -177,6 +177,9 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
CONSTANT c_wb_fifo_fill_offset : INTEGER := 2; -- some offset to adjust the mean fifo fill level
CONSTANT c_wb_sync_in_latency : NATURAL := 12; -- estimated nof dp_clk cycles latency of wb_sync transfer in the in_clk domain based on simulation and measurement on hardware
CONSTANT c_wb_sync_roundtrip : NATURAL := c_wb_fifo_fill_offset+g_dp_phs_clk_period/2; -- achieve this nof dp_clk cycles from getting wb_sync back via dp_sync
CONSTANT c_wb_sync_roundtrip_margin : NATURAL := 2;
CONSTANT c_wb_sync_roundtrip_max : NATURAL := c_wb_sync_roundtrip+c_wb_sync_roundtrip_margin;
CONSTANT c_wb_sync_roundtrip_min : NATURAL := c_wb_sync_roundtrip-c_wb_sync_roundtrip_margin;
CONSTANT c_wb_fifo_fill_level : NATURAL := c_wb_fifo_fill_offset+c_wb_sync_roundtrip-c_wb_sync_in_latency; -- expected FIFO fill level on read side (mean level +- 1 can occur),
CONSTANT c_wb_fifo_fill_margin : NATURAL := 2; -- some symmetrical FIFO filled margin >= 0, use 0 in theory, use 1 to allow some timing uncertainty in rdusedw of dual clock FIFO
CONSTANT c_wb_fifo_fill_margin_p : NATURAL := c_wb_fifo_fill_margin; -- some FIFO more filled margin >= 0, use 0 or 1 to allow 8 and 9
......@@ -196,6 +199,7 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
SIGNAL dbg_status_0_out_word_locked : STD_LOGIC;
SIGNAL dbg_status_1_out_word_stable : STD_LOGIC;
SIGNAL dbg_status_3_dp_fifo_fill_stable : STD_LOGIC;
SIGNAL dbg_status_4_dp_phs_locked : STD_LOGIC;
SIGNAL dbg_status_5_wb_roundtrip_stable : STD_LOGIC;
SIGNAL dbg_status_6_dp_in_clk_detected : STD_LOGIC;
......@@ -287,6 +291,8 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
SIGNAL fifo_rd_val : STD_LOGIC;
SIGNAL fifo_rd_emp : STD_LOGIC;
SIGNAL fifo_rdusedw : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);
SIGNAL dp_fifo_fill_lock : STD_LOGIC;
SIGNAL dp_fifo_fill_stable : STD_LOGIC;
SIGNAL dp_phs_clk_en_vec_evt : STD_LOGIC;
SIGNAL dp_phs_timeout_cnt : STD_LOGIC_VECTOR(c_dp_dd_phs_timeout_w-1 DOWNTO 0);
......@@ -294,6 +300,7 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
SIGNAL dp_phs_timeout : STD_LOGIC;
SIGNAL dp_phs_val : STD_LOGIC;
SIGNAL dp_phs_lock_lost : STD_LOGIC;
SIGNAL dp_phs_stable : STD_LOGIC;
SIGNAL dp_phs_align_restart : STD_LOGIC;
SIGNAL dp_phs_align_restart_extend : STD_LOGIC;
......@@ -302,6 +309,7 @@ ARCHITECTURE str OF lvdsh_dd_phs4 IS
SIGNAL wb_phs_clk : STD_LOGIC;
SIGNAL wb_sync_cap : STD_LOGIC;
SIGNAL wb_cnt : STD_LOGIC_VECTOR(c_wb_cnt_w-1 DOWNTO 0);
SIGNAL wb_roundtrip_expected : STD_LOGIC;
SIGNAL wb_roundtrip_lock : STD_LOGIC;
SIGNAL wb_roundtrip_stable : STD_LOGIC;
......@@ -641,10 +649,10 @@ BEGIN
nxt_r_dp.dp_word_req_dly(c_word_req_lat-1 DOWNTO 0) <= r_dp.dp_word_req_dly(c_word_req_lat-2 DOWNTO 0) & r_dp.dp_word_req;
-- Monitor wb_cnt of roundtrip latency
wb_roundtrip_lock <= '1' WHEN UNSIGNED(r_dp.wb_cnt_roundtrip)=c_wb_sync_roundtrip ELSE '0';
-- Detect expected wb_cnt of roundtrip latency
wb_roundtrip_expected <= '1' WHEN UNSIGNED(r_dp.wb_cnt_roundtrip)=c_wb_sync_roundtrip ELSE '0';
p_dp_word_lock : PROCESS (r_dp, wb_cnt, wb_roundtrip_lock, fifo_rd_emp, fifo_rdusedw)
p_dp_word_lock : PROCESS (r_dp, wb_cnt, wb_roundtrip_expected, fifo_rd_emp, fifo_rdusedw)
BEGIN
nxt_r_dp.wb_cnt_clr <= '1';
nxt_r_dp.wb_cnt_roundtrip <= (OTHERS=>'0');
......@@ -700,7 +708,7 @@ BEGIN
-- *** Word locked, this is the correct end state for the ALIGNED data processing ***
-- Fine check roundtrip latency during stable word lock
IF wb_roundtrip_lock='0' AND r_dp.dp_maintain_phs = '0' THEN
IF wb_roundtrip_expected='0' AND r_dp.dp_maintain_phs = '0' THEN
-- After achieving dp_word_locked, but while dp_maintain_phs is still '0' the wb_cnt_roundtrip must exactly match c_wb_sync_roundtrip.
nxt_r_dp.dp_word_lock_failed <= '1'; -- word lock lost, so recover via in_rst
END IF;
......@@ -740,7 +748,7 @@ BEGIN
END IF;
-- Course check roundtrip latency and FIFO fill level at any time
IF UNSIGNED(wb_cnt) > c_wb_sync_roundtrip+1 THEN
IF UNSIGNED(wb_cnt) > c_wb_sync_roundtrip_max THEN
nxt_r_dp.dp_word_lock_failed <= '1'; -- timeout dp_sync, so recover via in_rst
END IF;
IF UNSIGNED(fifo_rdusedw) > c_wb_fifo_fill_max THEN
......@@ -748,6 +756,13 @@ BEGIN
END IF;
END PROCESS;
-- Monitor wb_cnt of roundtrip latency, use >min and <max instead of >=min and <=max to over constrain it compared to the checks in p_dp_word_lock
wb_roundtrip_lock <= '1' WHEN UNSIGNED(r_dp.wb_cnt_roundtrip)>=c_wb_sync_roundtrip_min AND UNSIGNED(r_dp.wb_cnt_roundtrip)<=c_wb_sync_roundtrip_max ELSE '0';
-- Monitor fifo_rdusedw, use >min and <max instead of >=min and <=max to over constrain it compared to the checks in p_dp_word_lock
dp_fifo_fill_lock <= '1' WHEN UNSIGNED(fifo_rdusedw) > c_wb_fifo_fill_min AND UNSIGNED(fifo_rdusedw) < c_wb_fifo_fill_max ELSE '0';
------------------------------------------------------------------------------
-- Monitor the dp_clk phase alignment
------------------------------------------------------------------------------
......@@ -756,7 +771,8 @@ BEGIN
BEGIN
-- Debug monitor status
i_out_status <= (OTHERS=>'0');
i_out_status( 4) <= r_dp.dp_phs_locked; -- 1 bit
i_out_status( 3) <= dp_fifo_fill_stable; -- 1 bit
i_out_status( 4) <= dp_phs_stable; -- 1 bit
i_out_status( 5) <= wb_roundtrip_stable; -- 1 bit
i_out_status( 7 DOWNTO 6) <= dp_in_clk_stable & dp_in_clk_detected; -- 2 bit
i_out_status(15 DOWNTO 8) <= fifo_rdusedw; -- c_fifo_size_w = 8
......@@ -770,6 +786,7 @@ BEGIN
sim_dbg_status : IF g_sim=TRUE GENERATE
dbg_status_0_out_word_locked <= r_dp.dp_word_locked;
dbg_status_1_out_word_stable <= i_out_word_stable;
dbg_status_3_dp_fifo_fill_stable <= i_out_status(3);
dbg_status_4_dp_phs_locked <= i_out_status(4);
dbg_status_5_wb_roundtrip_stable <= i_out_status(5);
dbg_status_6_dp_in_clk_detected <= i_out_status(6);
......@@ -780,23 +797,47 @@ BEGIN
dbg_status_31_28_dp_raw_phs <= i_out_status(31 DOWNTO 28) WHEN r_dp.dp_val='1' AND r_dp.le_val='1'; -- latch to view only yhe raw_phs when in lock
END GENERATE;
------------------------------------------------------------------------------
-- Stable monitors for out_status
------------------------------------------------------------------------------
u_common_stable_monitor_word_lock : ENTITY common_lib.common_stable_monitor
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- MM
r_in => r_dp.dp_word_locked,
r_stable => i_out_word_stable,
r_stable => i_out_word_stable, -- monitors lvdsh_dd_phs4 overalll data output stable (both phs and word)
r_stable_ack => out_word_stable_ack
);
u_common_stable_monitor_phs_lock : ENTITY common_lib.common_stable_monitor
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- MM
r_in => r_dp.dp_phs_locked,
r_stable => dp_phs_stable, -- monitors lvdsh_dd_phs4_align data output stable
r_stable_ack => out_word_stable_ack
);
u_common_stable_monitor_fifo_fill_lock : ENTITY common_lib.common_stable_monitor
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- MM
r_in => dp_fifo_fill_lock,
r_stable => dp_fifo_fill_stable, -- monitors FIFO fill level between min and max
r_stable_ack => out_word_stable_ack
);
u_common_stable_monitor_wb_cnt_roundtrip : ENTITY common_lib.common_stable_monitor
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- MM
r_in => wb_roundtrip_lock,
r_stable => wb_roundtrip_stable,
r_stable => wb_roundtrip_stable, -- monitors roundtrip latency of wb_sync --> dp_sync via in_clk domain between +-1
r_stable_ack => out_word_stable_ack
);
......
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