Add xon flow control when FIFO is almost full at block level.

libraries/base/dp/src/vhdl/dp_fifo_core.vhd

@@ -66,7 +66,8 @@ ENTITY dp_fifo_core IS
     g_use_ctrl       : BOOLEAN := TRUE;  -- sop & eop
     g_use_complex    : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_size      : NATURAL := 512;   -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1
   );
   PORT (
@@ -97,6 +98,7 @@ ARCHITECTURE str OF dp_fifo_core IS
   CONSTANT c_complex_w        : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2);  -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
    
   CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size - g_fifo_af_margin;  -- FIFO almost full level for snk_out.ready
+  CONSTANT c_fifo_almost_xon  : NATURAL := g_fifo_size - g_fifo_af_xon;     -- FIFO almost full level for snk_out.xon
   CONSTANT c_fifo_dat_w       : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
                                                              g_data_w,   g_bsn_w,   g_empty_w,   g_channel_w,   g_error_w,   1,          c_ctrl_w);  -- concat via FIFO
   
@@ -163,8 +165,9 @@ BEGIN
                                  wr_sync,
                                  wr_ctrl);
   
-  -- pass on frame level flow control
-  nxt_snk_out.xon <= src_in.xon;
+  -- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
+  -- add flow contol dependent on whether the fifo can fit another block
+  nxt_snk_out.xon <= src_in.xon WHEN UNSIGNED(fifo_wr_usedw) <= c_fifo_almost_xon ELSE '0';
 
   -- up stream use fifo almost full to control snk_out.ready
   nxt_snk_out.ready <= NOT wr_init WHEN UNSIGNED(fifo_wr_usedw) < c_fifo_almost_full ELSE '0';

libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd

@@ -73,7 +73,8 @@ ENTITY dp_fifo_core_arr IS
     g_use_ctrl       : BOOLEAN := TRUE;  -- sop & eop
     g_use_complex    : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_size      : NATURAL := 512;   -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1
   );
   PORT (
@@ -107,6 +108,7 @@ ARCHITECTURE str OF dp_fifo_core_arr IS
   CONSTANT c_complex_w        : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2);  -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
    
   CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size - g_fifo_af_margin;  -- FIFO almost full level for snk_out.ready
+  CONSTANT c_fifo_almost_xon  : NATURAL := g_fifo_size - g_fifo_af_xon;     -- FIFO almost full level for snk_out.xon
   CONSTANT c_fifo_dat_w       : NATURAL := func_slv_concat_w(c_use_data,     g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
                                                              c_total_data_w, g_bsn_w,   g_empty_w,   g_channel_w,   g_error_w,   1,          c_ctrl_w,   g_aux_w);  -- concat via FIFO
   
@@ -185,10 +187,11 @@ BEGIN
                                  wr_ctrl,
                                  wr_aux);
   
-  -- pass on frame level flow control
-  nxt_snk_out.xon <= src_in_arr(0).xon;
+  -- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
+  -- add flow contol dependent on whether the fifo can fit another block
+  nxt_snk_out.xon <= src_in_arr(0).xon WHEN UNSIGNED(fifo_wr_usedw) <= c_fifo_almost_xon ELSE '0';
 
-  -- up stream use fifo almost full to control snk_out.ready
+  -- use fifo almost full to control up stream snk_out.ready
   nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw) < c_fifo_almost_full ELSE '0';
     
   gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE

libraries/base/dp/src/vhdl/dp_fifo_dc.vhd

@@ -46,7 +46,8 @@ ENTITY dp_fifo_dc IS
     g_use_ctrl       : BOOLEAN := TRUE;  -- sop & eop
     g_use_complex    : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_size      : NATURAL := 512;   -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1
   );
   PORT (
@@ -91,6 +92,7 @@ BEGIN
     g_use_complex    => g_use_complex,
     g_fifo_size      => g_fifo_size,
     g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_af_xon    => g_fifo_af_xon,
     g_fifo_rl        => g_fifo_rl
   )
   PORT MAP (

libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd

@@ -51,7 +51,8 @@ ENTITY dp_fifo_dc_arr IS
     g_use_ctrl       : BOOLEAN := TRUE;  -- sop & eop
     g_use_complex    : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_size      : NATURAL := 512;   -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1
   );
   PORT (
@@ -101,6 +102,7 @@ BEGIN
     g_use_complex    => g_use_complex,
     g_fifo_size      => g_fifo_size,
     g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_af_xon    => g_fifo_af_xon,
     g_fifo_rl        => g_fifo_rl
   )
   PORT MAP (

libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd

@@ -114,7 +114,8 @@ ENTITY dp_fifo_dc_mixed_widths IS
     g_rd_data_w         : NATURAL := 9;
     g_use_ctrl          : BOOLEAN := TRUE;
     g_wr_fifo_size      : NATURAL := 512;   -- FIFO size in nof wr_data words
-    g_wr_fifo_af_margin : NATURAL := 4;     --  >=4, Nof words below max (full) at which fifo is considered almost full
+    g_wr_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_wr_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_rd_fifo_rl        : NATURAL := 1
   );
   PORT (
@@ -151,6 +152,7 @@ ARCHITECTURE str OF dp_fifo_dc_mixed_widths IS
   CONSTANT c_empty_w             : NATURAL := ceil_log2(c_nof_narrow);
   
   CONSTANT c_fifo_wr_almost_full : NATURAL := g_wr_fifo_size - g_wr_fifo_af_margin;  -- FIFO almost full level for snk_out.ready
+  CONSTANT c_fifo_wr_almost_xon  : NATURAL := g_wr_fifo_size - g_wr_fifo_af_xon;     -- FIFO almost full level for snk_out.xon
 
   CONSTANT c_fifo_narrow_data_w  : NATURAL := c_narrow_data_w + c_ctrl_w;           -- if used concat control via FIFO
   CONSTANT c_fifo_wide_data_w    : NATURAL := c_nof_narrow * c_fifo_narrow_data_w;  -- all through one FIFO
@@ -185,6 +187,7 @@ ARCHITECTURE str OF dp_fifo_dc_mixed_widths IS
   SIGNAL rd_sosi        : t_dp_sosi := c_dp_sosi_rst;  -- initialize default values for unused sosi fields
   
   SIGNAL i_snk_out      : t_dp_siso := c_dp_siso_rst;
+  SIGNAL nxt_snk_out    : t_dp_siso := c_dp_siso_rst;
 
 BEGIN
 
@@ -245,15 +248,18 @@ BEGIN
     BEGIN
       IF wr_rst='1' THEN
         fifo_aful     <= '0';
+        i_snk_out.xon <= '0';
       ELSIF rising_edge(wr_clk) THEN
         fifo_aful     <= nxt_fifo_aful;
+        i_snk_out.xon <= nxt_snk_out.xon;
       END IF;
     END PROCESS;
     
     -- Padding is only needed for the narrow write with frame control, in all other cases the padding control defaults to the redundant initialisation values
     
-    -- pass on frame level flow control
-    i_snk_out.xon <= src_in.xon;
+    -- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
+    -- add flow contol dependent on whether the fifo can fit another block
+    nxt_snk_out.xon <= src_in.xon WHEN UNSIGNED(i_wr_usedw) <= c_fifo_wr_almost_xon ELSE '0';
 
     -- use FIFO almost full and no padding going on to control output ready to up stream
     i_snk_out.ready <= (NOT fifo_aful) AND wr_pad_ready;

libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd

@@ -81,7 +81,8 @@ ENTITY dp_fifo_fill_core IS
     g_use_complex    : BOOLEAN := FALSE;  -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_fill      : NATURAL := 0;
     g_fifo_size      : NATURAL := 256;    -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;      -- Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1       -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
   );
   PORT (
@@ -176,6 +177,7 @@ BEGIN
       g_use_complex    => g_use_complex,
       g_fifo_size      => c_fifo_size,
       g_fifo_af_margin => g_fifo_af_margin,
+      g_fifo_af_xon    => g_fifo_af_xon,
       g_fifo_rl        => c_fifo_rl
     )
     PORT MAP (
@@ -215,6 +217,7 @@ BEGIN
       --g_use_complex    => g_use_complex,
       g_fifo_size      => c_fifo_size,
       g_fifo_af_margin => g_fifo_af_margin,
+      g_fifo_af_xon    => g_fifo_af_xon,
       g_fifo_rl        => c_fifo_rl
     )
     PORT MAP (

libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd

@@ -76,7 +76,8 @@ ENTITY dp_fifo_fill_eop IS
     g_use_complex    : BOOLEAN := FALSE;  -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_fill      : NATURAL := 0;
     g_fifo_size      : NATURAL := 256;    -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;      -- Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1       -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
   );
   PORT (
@@ -185,6 +186,7 @@ BEGIN
     g_use_complex    => g_use_complex,
     g_fifo_size      => c_fifo_size,
     g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_af_xon    => g_fifo_af_xon,
     g_fifo_rl        => c_fifo_rl
   )
   PORT MAP (

libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd

@@ -47,7 +47,8 @@ ENTITY dp_fifo_fill_sc IS
     g_use_complex    : BOOLEAN := FALSE;  -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_fill      : NATURAL := 0;
     g_fifo_size      : NATURAL := 256;    -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;      -- Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1       -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
   );
   PORT (
@@ -96,6 +97,7 @@ BEGIN
     g_fifo_fill      => g_fifo_fill,
     g_fifo_size      => g_fifo_size,
     g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_af_xon    => g_fifo_af_xon,
     g_fifo_rl        => g_fifo_rl       
   )
   PORT MAP (

libraries/base/dp/src/vhdl/dp_fifo_sc.vhd

@@ -48,7 +48,8 @@ ENTITY dp_fifo_sc IS
     g_use_ctrl       : BOOLEAN := TRUE;  -- sop & eop
     g_use_complex    : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
     g_fifo_size      : NATURAL := 512;   -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
-    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+    g_fifo_af_xon    : NATURAL := 0;     -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
     g_fifo_rl        : NATURAL := 1
   );
   PORT (
@@ -92,6 +93,7 @@ BEGIN
     g_use_complex    => g_use_complex,
     g_fifo_size      => g_fifo_size,
     g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_af_xon    => g_fifo_af_xon,
     g_fifo_rl        => g_fifo_rl
   )
   PORT MAP (