diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index c8f9cb39db358df72a7a0fbd4ab161343a341e54..63085ac767e85f9dc04689ea1038483e9d5e58e1 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -66,7 +66,8 @@ ENTITY dp_fifo_core IS
g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1
);
PORT (
@@ -96,7 +97,8 @@ ARCHITECTURE str OF dp_fifo_core IS
CONSTANT c_complex_w : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
- CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_almost_xon : NATURAL := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
CONSTANT c_fifo_dat_w : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
@@ -163,11 +165,12 @@ BEGIN
wr_sync,
wr_ctrl);
- -- pass on frame level flow control
- nxt_snk_out.xon <= src_in.xon;
+ -- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
+ -- add flow contol dependent on whether the fifo can fit another block
+ nxt_snk_out.xon <= src_in.xon WHEN UNSIGNED(fifo_wr_usedw) <= c_fifo_almost_xon ELSE '0';
-- up stream use fifo almost full to control snk_out.ready
- nxt_snk_out.ready <= NOT wr_init WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
+ nxt_snk_out.ready <= NOT wr_init WHEN UNSIGNED(fifo_wr_usedw) < c_fifo_almost_full ELSE '0';
gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
index 83964e22b64cf0a3cdc95ad955082f8752e7d713..d74579e00f221eeaf386a55abde1a43f0ae4629d 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -73,7 +73,8 @@ ENTITY dp_fifo_core_arr IS
g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1
);
PORT (
@@ -106,7 +107,8 @@ ARCHITECTURE str OF dp_fifo_core_arr IS
CONSTANT c_complex_w : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
- CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_almost_xon : NATURAL := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
CONSTANT c_fifo_dat_w : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
@@ -185,11 +187,12 @@ BEGIN
wr_ctrl,
wr_aux);
- -- pass on frame level flow control
- nxt_snk_out.xon <= src_in_arr(0).xon;
+ -- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
+ -- add flow contol dependent on whether the fifo can fit another block
+ nxt_snk_out.xon <= src_in_arr(0).xon WHEN UNSIGNED(fifo_wr_usedw) <= c_fifo_almost_xon ELSE '0';
- -- up stream use fifo almost full to control snk_out.ready
- nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
+ -- use fifo almost full to control up stream snk_out.ready
+ nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw) < c_fifo_almost_full ELSE '0';
gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index f5638052d7af7f99ebf06a4c0482791d13ac3639..211b97800f7e6bea6b800c3bbef87afe6374e13f 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -46,7 +46,8 @@ ENTITY dp_fifo_dc IS
g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1
);
PORT (
@@ -91,6 +92,7 @@ BEGIN
g_use_complex => g_use_complex,
g_fifo_size => g_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => g_fifo_rl
)
PORT MAP (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index 45d65e14cda439a068b419d049d6bc5db4ae507e..dcfd02e39c891d8211aadc39a74297d9410ac21c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -51,7 +51,8 @@ ENTITY dp_fifo_dc_arr IS
g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1
);
PORT (
@@ -101,6 +102,7 @@ BEGIN
g_use_complex => g_use_complex,
g_fifo_size => g_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => g_fifo_rl
)
PORT MAP (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
index 5b809003534f71183cafea90a0795368cd517104..996f267d282d660faa82c1291f34a371b47edf2a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
@@ -114,7 +114,8 @@ ENTITY dp_fifo_dc_mixed_widths IS
g_rd_data_w : NATURAL := 9;
g_use_ctrl : BOOLEAN := TRUE;
g_wr_fifo_size : NATURAL := 512; -- FIFO size in nof wr_data words
- g_wr_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_wr_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_wr_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_rd_fifo_rl : NATURAL := 1
);
PORT (
@@ -150,8 +151,9 @@ ARCHITECTURE str OF dp_fifo_dc_mixed_widths IS
CONSTANT c_ctrl_w : NATURAL := sel_a_b(g_use_ctrl, 2, 0); -- sop and eop, or no ctrl
CONSTANT c_empty_w : NATURAL := ceil_log2(c_nof_narrow);
- CONSTANT c_fifo_wr_almost_full : NATURAL := g_wr_fifo_size-g_wr_fifo_af_margin; -- FIFO almost full level for snk_out.ready
-
+ CONSTANT c_fifo_wr_almost_full : NATURAL := g_wr_fifo_size - g_wr_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_wr_almost_xon : NATURAL := g_wr_fifo_size - g_wr_fifo_af_xon; -- FIFO almost full level for snk_out.xon
+
CONSTANT c_fifo_narrow_data_w : NATURAL := c_narrow_data_w + c_ctrl_w; -- if used concat control via FIFO
CONSTANT c_fifo_wide_data_w : NATURAL := c_nof_narrow * c_fifo_narrow_data_w; -- all through one FIFO
@@ -185,7 +187,8 @@ ARCHITECTURE str OF dp_fifo_dc_mixed_widths IS
SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields
SIGNAL i_snk_out : t_dp_siso := c_dp_siso_rst;
-
+ SIGNAL nxt_snk_out : t_dp_siso := c_dp_siso_rst;
+
BEGIN
-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
@@ -239,21 +242,24 @@ BEGIN
wr_ful <= fifo_wr_ful;
wr_usedw <= i_wr_usedw;
- nxt_fifo_aful <= '0' WHEN (UNSIGNED(i_wr_usedw)<c_fifo_wr_almost_full) ELSE '1';
-
+ nxt_fifo_aful <= '0' WHEN (UNSIGNED(i_wr_usedw) < c_fifo_wr_almost_full) ELSE '1';
+
p_wr_clk: PROCESS(wr_clk, wr_rst)
BEGIN
IF wr_rst='1' THEN
- fifo_aful <= '0';
+ fifo_aful <= '0';
+ i_snk_out.xon <= '0';
ELSIF rising_edge(wr_clk) THEN
- fifo_aful <= nxt_fifo_aful;
+ fifo_aful <= nxt_fifo_aful;
+ i_snk_out.xon <= nxt_snk_out.xon;
END IF;
END PROCESS;
-- Padding is only needed for the narrow write with frame control, in all other cases the padding control defaults to the redundant initialisation values
- -- pass on frame level flow control
- i_snk_out.xon <= src_in.xon;
+ -- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
+ -- add flow contol dependent on whether the fifo can fit another block
+ nxt_snk_out.xon <= src_in.xon WHEN UNSIGNED(i_wr_usedw) <= c_fifo_wr_almost_xon ELSE '0';
-- use FIFO almost full and no padding going on to control output ready to up stream
i_snk_out.ready <= (NOT fifo_aful) AND wr_pad_ready;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index ef89bbe4222771651c94497ecb019d0dd2280efb..cf1157ef538a3629b752ae022ae492e0c710bf72 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -81,7 +81,8 @@ ENTITY dp_fifo_fill_core IS
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_fill : NATURAL := 0;
g_fifo_size : NATURAL := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
);
PORT (
@@ -176,6 +177,7 @@ BEGIN
g_use_complex => g_use_complex,
g_fifo_size => c_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => c_fifo_rl
)
PORT MAP (
@@ -215,6 +217,7 @@ BEGIN
--g_use_complex => g_use_complex,
g_fifo_size => c_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => c_fifo_rl
)
PORT MAP (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 9d904f89e2cf577428a406bc5ee0fb2b1530b9f6..709af7d621a57d40fea76c96079df3820cb80717 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -76,7 +76,8 @@ ENTITY dp_fifo_fill_eop IS
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_fill : NATURAL := 0;
g_fifo_size : NATURAL := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
);
PORT (
@@ -185,6 +186,7 @@ BEGIN
g_use_complex => g_use_complex,
g_fifo_size => c_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => c_fifo_rl
)
PORT MAP (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index db85d766fdeb1160ec49358fa622ac9e23bb66c8..dd7fa79f5910ad055dfbc994559513489ccda944 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -47,7 +47,8 @@ ENTITY dp_fifo_fill_sc IS
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_fill : NATURAL := 0;
g_fifo_size : NATURAL := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
);
PORT (
@@ -96,6 +97,7 @@ BEGIN
g_fifo_fill => g_fifo_fill,
g_fifo_size => g_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => g_fifo_rl
)
PORT MAP (
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index fb9570775d09d98e39f905748c21ad9ea61c5feb..3f261029443d6ad6de693bd149033c1fcf749052 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -48,7 +48,8 @@ ENTITY dp_fifo_sc IS
g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1
);
PORT (
@@ -92,6 +93,7 @@ BEGIN
g_use_complex => g_use_complex,
g_fifo_size => g_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => g_fifo_rl
)
PORT MAP (