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Commit 35a54c75 authored by Eric Kooistra's avatar Eric Kooistra
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Name and comment chanegs only.

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1 merge request!330Resolve L2SDP-942
Pipeline #48647 passed
......@@ -369,7 +369,7 @@ ENTITY sdp_station IS
reg_nw_10GbE_eth10g_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- QSFP for beamlet output and for ring cable
-- QSFP[1] quad for beamlet output and QSFP[0] quad for ring cable
----------------------------------------------
-- QSFP serial (6 QSFP ports per FPGA)
......@@ -444,12 +444,16 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_fifo_tx_size_ring : NATURAL := true_log_pow2(c_lane_packet_nof_longwords_max + c_fifo_tx_fill_margin); -- = 552 + 6 --> 1024
CONSTANT c_fifo_tx_fill_ring : NATURAL := c_fifo_tx_size_ring - c_fifo_tx_fill_margin; -- = maximum fill level, so rely on eop
CONSTANT c_nof_lane : NATURAL := 3; -- 0 = XST, 1 = BF_0, 2 = BF_1.
CONSTANT c_nof_if : NATURAL := 3; -- 3 different interfaces, QSFP, RING_0 and RING_1
CONSTANT c_qsfp_if_offset : NATURAL := 0; -- QSFP signals are indexed at c_nof_if * I.
CONSTANT c_ring_0_if_offset : NATURAL := 1; -- RING_0 signals are indexed at c_nof_if * I + 1.
CONSTANT c_ring_1_if_offset : NATURAL := 2; -- RING_1 signals are indexed at c_nof_if * I + 2.
CONSTANT c_ring_nof_mac : NATURAL := 12; -- Using 9 out of 12 (this is NOT optimized away during synthesis), must match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
CONSTANT c_nof_even_lanes : NATURAL := 3; -- 0 = XST, 1 = BF_0, 2 = BF_1.
CONSTANT c_lane_nof_if : NATURAL := 3; -- 3 different 10GbE interfaces per pair of lanes: QSFP cable, RING_0 pcb and RING_1 pcb
CONSTANT c_ring_qsfp_if_offset : NATURAL := 0; -- QSFP cable signals are indexed at c_lane_nof_if * I.
CONSTANT c_ring_0_if_offset : NATURAL := 1; -- RING_0 pcb signals are indexed at c_lane_nof_if * I + 1.
CONSTANT c_ring_1_if_offset : NATURAL := 2; -- RING_1 pcb signals are indexed at c_lane_nof_if * I + 2.
CONSTANT c_ring_nof_mac : NATURAL := c_nof_even_lanes * c_lane_nof_if;
-- Using c_ring_nof_mac out of 12 (this is NOT optimized away during synthesis), must
-- match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
CONSTANT c_ring_nof_mac_ip : NATURAL := 12; -- >= c_ring_nof_mac
TYPE t_dp_sosi_2arr_pfb IS ARRAY (INTEGER RANGE <>) OF t_dp_sosi_arr(c_sdp_P_pfb - 1 DOWNTO 0);
......@@ -549,10 +553,10 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL xst_to_ri_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bf_from_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL bf_to_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL lane_tx_board_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0);
SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0);
SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0);
SIGNAL lane_tx_board_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes-1 DOWNTO 0);
SIGNAL dp_bsn_source_restart : STD_LOGIC; -- used to restart WPFB sync interval timing
SIGNAL dp_bsn_source_new_interval : STD_LOGIC; -- used to mask out first sync interval for SST and BST offload
......@@ -567,13 +571,13 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL tr_ref_rst_156 : STD_LOGIC;
-- 10GbE ring
SIGNAL tr_10gbe_ring_serial_tx_arr : STD_LOGIC_VECTOR(c_ring_nof_mac-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tr_10gbe_ring_serial_rx_arr : STD_LOGIC_VECTOR(c_ring_nof_mac-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tr_10gbe_ring_serial_tx_arr : STD_LOGIC_VECTOR(c_ring_nof_mac_ip-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tr_10gbe_ring_serial_rx_arr : STD_LOGIC_VECTOR(c_ring_nof_mac_ip-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tr_10gbe_ring_snk_in_arr : t_dp_sosi_arr(c_ring_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL tr_10gbe_ring_snk_out_arr : t_dp_siso_arr(c_ring_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL tr_10gbe_ring_src_out_arr : t_dp_sosi_arr(c_ring_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL tr_10gbe_ring_src_in_arr : t_dp_siso_arr(c_ring_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL tr_10gbe_ring_snk_in_arr : t_dp_sosi_arr(c_ring_nof_mac_ip-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL tr_10gbe_ring_snk_out_arr : t_dp_siso_arr(c_ring_nof_mac_ip-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL tr_10gbe_ring_src_out_arr : t_dp_sosi_arr(c_ring_nof_mac_ip-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL tr_10gbe_ring_src_in_arr : t_dp_siso_arr(c_ring_nof_mac_ip-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- 10GbE beamlet output
SIGNAL nw_10gbe_beamlet_output_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_beamlet_output-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
......@@ -1160,7 +1164,7 @@ BEGIN
);
---------------
-- nw_10GbE beamlet output
-- nw_10GbE beamlet output via front_io QSFP[1]
---------------
u_nw_10GbE_beamlet_output: ENTITY nw_10GbE_lib.nw_10GbE
GENERIC MAP (
......@@ -1373,31 +1377,32 @@ BEGIN
miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
);
END GENERATE;
-----------------------------------------------------------------------------
-- Combine seperate signals into array for tr_10GbE
-----------------------------------------------------------------------------
gen_lane_wires : FOR I IN 0 TO c_nof_lane-1 GENERATE
gen_lane_wires : FOR I IN 0 TO c_nof_even_lanes-1 GENERATE
-- QSFP_RX, use_cable_to_previous_rn=1 -> even lanes receive from cable
lane_rx_cable_sosi_arr(I) <= tr_10gbe_ring_src_out_arr(c_nof_if * I + c_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst;
lane_rx_cable_sosi_arr(I) <= tr_10gbe_ring_src_out_arr(c_lane_nof_if * I + c_ring_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst;
-- QSFP_TX, use_cable_to_next_rn=1 -> even lanes transmit to cable
tr_10gbe_ring_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_sosi_arr(I) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst;
tr_10gbe_ring_snk_in_arr(c_lane_nof_if * I + c_ring_qsfp_if_offset) <= lane_tx_cable_sosi_arr(I) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst;
-- RING_0_RX even lanes receive from RING_0 (from the left)
lane_rx_board_sosi_arr(I) <= tr_10gbe_ring_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
lane_rx_board_sosi_arr(I) <= tr_10gbe_ring_src_out_arr(c_lane_nof_if * I + c_ring_0_if_offset);
-- RING_1_TX even lanes transmit to RING_1 (to the right)
tr_10gbe_ring_snk_in_arr(c_nof_if * I + c_ring_1_if_offset) <= lane_tx_board_sosi_arr(I);
tr_10gbe_ring_snk_in_arr(c_lane_nof_if * I + c_ring_1_if_offset) <= lane_tx_board_sosi_arr(I);
END GENERATE;
-----------------------------------------------------------------------------
-- tr_10GbE ring
-- tr_10GbE ring via front_io QSFP[0]
-----------------------------------------------------------------------------
u_tr_10GbE_ring: ENTITY tr_10GbE_lib.tr_10GbE
GENERIC MAP (
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => c_ring_nof_mac,
g_nof_macs => c_ring_nof_mac_ip,
g_direction => "TX_RX",
g_tx_fifo_fill => c_fifo_tx_fill_ring,
g_tx_fifo_size => c_fifo_tx_size_ring
......@@ -1437,23 +1442,23 @@ BEGIN
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
-----------------------------------------------------------------------------
-- Seperating the one large serial tx/rx array from tr_10GbE to the 3 port arrays:
-- QSFP port, RING_0 port and RING_1 port.
gen_serial_wires : FOR I IN 0 TO c_nof_lane-1 GENERATE
-- Seperating the one large serial tx/rx array from tr_10GbE to the c_lane_nof_if = 3
-- port arrays: QSFP cable port, RING_0 pcb port and RING_1 pcb port.
gen_ring_serial_wires : FOR I IN 0 TO c_nof_even_lanes-1 GENERATE
-- QSFP_TX
unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_ring_serial_tx_arr(c_nof_if * I + c_qsfp_if_offset);
unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_ring_serial_tx_arr(c_lane_nof_if * I + c_ring_qsfp_if_offset);
-- QSFP_RX
tr_10gbe_ring_serial_rx_arr(c_nof_if * I + c_qsfp_if_offset) <= unb2_board_front_io_serial_rx_arr(I);
tr_10gbe_ring_serial_rx_arr(c_lane_nof_if * I + c_ring_qsfp_if_offset) <= unb2_board_front_io_serial_rx_arr(I);
-- RING_0_TX
RING_0_TX(I) <= tr_10gbe_ring_serial_tx_arr(c_nof_if * I + c_ring_0_if_offset);
RING_0_TX(I) <= tr_10gbe_ring_serial_tx_arr(c_lane_nof_if * I + c_ring_0_if_offset);
-- RING_0_RX
tr_10gbe_ring_serial_rx_arr(c_nof_if * I + c_ring_0_if_offset) <= RING_0_RX(I);
tr_10gbe_ring_serial_rx_arr(c_lane_nof_if * I + c_ring_0_if_offset) <= RING_0_RX(I);
-- RING_1_TX
RING_1_TX(I) <= tr_10gbe_ring_serial_tx_arr(c_nof_if * I + c_ring_1_if_offset);
RING_1_TX(I) <= tr_10gbe_ring_serial_tx_arr(c_lane_nof_if * I + c_ring_1_if_offset);
-- RING_1_RX
tr_10gbe_ring_serial_rx_arr(c_nof_if * I + c_ring_1_if_offset) <= RING_1_RX(I);
tr_10gbe_ring_serial_rx_arr(c_lane_nof_if * I + c_ring_1_if_offset) <= RING_1_RX(I);
END GENERATE;
END GENERATE;
......
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