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Commit 51612a83 authored by Eric Kooistra's avatar Eric Kooistra
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No need to use ip/ and no need to use *_top.vhd.

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hdl_lib_name = ip_arria10_transceiver_pll_10g
hdl_library_clause_name = ip_arria10_transceiver_pll_10g_lib
hdl_lib_uses = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip/compile_ip.tcl
synth_files =
ip_arria10_transceiver_pll_10g_top.vhd
test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
quartus_qip_files =
generated/ip_arria10_transceiver_pll_10g.qip
hdl_lib_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip/compile_ip.tcl
synth_files =
test_bench_files =
quartus_qip_files =
generated/ip_arria10_transceiver_pll_10g.qip
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for generated ip_arria10_transceiver_pll_10g.vhd
-- Description:
-- This wrapper avoids the need to vmap the ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 library
-- in the technology independent library that instantiate this IP.
-- Remarks:
-- . Manually created from generated ip_arria10_transceiver_pll_10g.vhd.
library IEEE;
use IEEE.std_logic_1164.all;
library ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140;
entity ip_arria10_transceiver_pll_10g_top is
port (
pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
tx_serial_clk : out std_logic; -- tx_serial_clk.clk
pll_locked : out std_logic; -- pll_locked.pll_locked
pll_cal_busy : out std_logic -- pll_cal_busy.pll_cal_busy
);
end ip_arria10_transceiver_pll_10g_top;
architecture str of ip_arria10_transceiver_pll_10g_top is
begin
u_ip_arria10_transceiver_pll_10g : entity ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140.ip_arria10_transceiver_pll_10g
port map (
pll_powerdown => pll_powerdown, -- pll_powerdown.pll_powerdown
pll_refclk0 => pll_refclk0 , -- pll_refclk0.clk
tx_serial_clk => tx_serial_clk, -- tx_serial_clk.clk
pll_locked => pll_locked , -- pll_locked.pll_locked
pll_cal_busy => pll_cal_busy -- pll_cal_busy.pll_cal_busy
);
end str;
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