Skip to content
Snippets Groups Projects
Commit f9cb5b12 authored by Eric Kooistra's avatar Eric Kooistra
Browse files

No need to use ip/ and no need to use *_top.vhd.

parent 0a523708
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 18 additions and 158 deletions
libraries/technology/ip_arria10/phy_10gbase_r/README.txt
+ 11
− 12
View file @ f9cb5b12
......@@ -16,18 +16,18 @@ The phy_10gbase_r IP is new for Arria10. However it serves the similar purpose a
The generated IP is not kept in SVN, only the Qsys source file:
ip/ip_arria10_phy_10gbase_r.qsys
ip_arria10_phy_10gbase_r.qsys
Therefore first the IP needs to be generated using:
ip/generate_ip.sh
generate_ip.sh
3) Compilation, simulation and verification
The genrated IP also contains a msim_setup.tcl file that was used to manually create:
ip/compile_ip.tcl
compile_ip.tcl
This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
......@@ -36,20 +36,19 @@ This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code
No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
ip/generated/ip_arria10_phy_10gbase_r.qip
generated/ip_arria10_phy_10gbase_r.qip
is included in the ip/hdllib.cfg and contains what is needed to synthesize the IP.
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
5) Remarks
a) Generated ip_arria10_phy_10gbase_r.vhd uses IP specific library ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
The ip/hdllib.cfg defines the IP specific library to make it known:
a) Use generated IP specific library clause name
The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
specific library as library claus name to make it known:
hdl_lib_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
hdl_lib_name = ip_arria10_<lib_name>
hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
The ip_arria10_phy_10gbase_r_top.vhd wrapper makes the IP accessible via ip_arria10_phy_10gbase_r_lib, to
avoid that the IP specific library needs to be used at the technology independent level.
\ No newline at end of file
libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+ 7
− 6
View file @ f9cb5b12
hdl_lib_name = ip_arria10_phy_10gbase_r
hdl_library_clause_name = ip_arria10_phy_10gbase_r_lib
hdl_lib_uses = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
synth_files =
ip_arria10_phy_10gbase_r_top.vhd
test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r.qip
libraries/technology/ip_arria10/phy_10gbase_r/ip/hdllib.cfg deleted 100644 → 0
+ 0
− 17
View file @ 0a523708
hdl_lib_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/ip/compile_ip.tcl
synth_files =
test_bench_files =
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r.qip
libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd deleted 100644 → 0
+ 0
− 123
View file @ 0a523708
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for generated ip_arria10_phy_10gbase_r.vhd
-- Description:
-- This wrapper avoids the need to vmap the ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140 library
-- in the technology independent library that instantiate this IP.
-- Remarks:
-- . Manually created from generated ip_arria10_phy_10gbase_r.vhd.
library IEEE;
use IEEE.std_logic_1164.all;
library ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140;
entity ip_arria10_phy_10gbase_r_top is
port (
tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
tx_pma_div_clkout : out std_logic_vector(0 downto 0); -- tx_pma_div_clkout.clk
tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
rx_enh_blk_lock : out std_logic_vector(0 downto 0) -- rx_enh_blk_lock.rx_enh_blk_lock
);
end ip_arria10_phy_10gbase_r_top;
architecture str of ip_arria10_phy_10gbase_r_top is
begin
u_ip_arria10_phy_10gbase_r : entity ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140.ip_arria10_phy_10gbase_r
port map (
tx_analogreset => tx_analogreset , -- tx_analogreset.tx_analogreset
tx_digitalreset => tx_digitalreset , -- tx_digitalreset.tx_digitalreset
rx_analogreset => rx_analogreset , -- rx_analogreset.rx_analogreset
rx_digitalreset => rx_digitalreset , -- rx_digitalreset.rx_digitalreset
tx_cal_busy => tx_cal_busy , -- tx_cal_busy.tx_cal_busy
rx_cal_busy => rx_cal_busy , -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 => tx_serial_clk0 , -- tx_serial_clk0.clk
rx_cdr_refclk0 => rx_cdr_refclk0 , -- rx_cdr_refclk0.clk
tx_serial_data => tx_serial_data , -- tx_serial_data.tx_serial_data
rx_serial_data => rx_serial_data , -- rx_serial_data.rx_serial_data
rx_is_lockedtoref => rx_is_lockedtoref , -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => rx_is_lockedtodata , -- rx_is_lockedtodata.rx_is_lockedtodata
tx_coreclkin => tx_coreclkin , -- tx_coreclkin.clk
rx_coreclkin => rx_coreclkin , -- rx_coreclkin.clk
tx_clkout => tx_clkout , -- tx_clkout.clk
rx_clkout => rx_clkout , -- rx_clkout.clk
tx_parallel_data => tx_parallel_data , -- tx_parallel_data.tx_parallel_data
rx_parallel_data => rx_parallel_data , -- rx_parallel_data.rx_parallel_data
tx_pma_div_clkout => tx_pma_div_clkout , -- tx_pma_div_clkout.clk
tx_control => tx_control , -- tx_control.tx_control
tx_err_ins => tx_err_ins , -- tx_err_ins.tx_err_ins
unused_tx_parallel_data => unused_tx_parallel_data, -- unused_tx_parallel_data.unused_tx_parallel_data
unused_tx_control => unused_tx_control , -- unused_tx_control.unused_tx_control
rx_control => rx_control , -- rx_control.rx_control
unused_rx_parallel_data => unused_rx_parallel_data, -- unused_rx_parallel_data.unused_rx_parallel_data
unused_rx_control => unused_rx_control , -- unused_rx_control.unused_rx_control
tx_enh_data_valid => tx_enh_data_valid , -- tx_enh_data_valid.tx_enh_data_valid
tx_enh_fifo_full => tx_enh_fifo_full , -- tx_enh_fifo_full.tx_enh_fifo_full
tx_enh_fifo_pfull => tx_enh_fifo_pfull , -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
tx_enh_fifo_empty => tx_enh_fifo_empty , -- tx_enh_fifo_empty.tx_enh_fifo_empty
tx_enh_fifo_pempty => tx_enh_fifo_pempty , -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
rx_enh_data_valid => rx_enh_data_valid , -- rx_enh_data_valid.rx_enh_data_valid
rx_enh_fifo_full => rx_enh_fifo_full , -- rx_enh_fifo_full.rx_enh_fifo_full
rx_enh_fifo_empty => rx_enh_fifo_empty , -- rx_enh_fifo_empty.rx_enh_fifo_empty
rx_enh_fifo_del => rx_enh_fifo_del , -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_insert => rx_enh_fifo_insert , -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber => rx_enh_highber , -- rx_enh_highber.rx_enh_highber
rx_enh_blk_lock => rx_enh_blk_lock -- rx_enh_blk_lock.rx_enh_blk_lock
);
end str;
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment