excludes change (using 1600 for ddr4)

4c145905 · Kenneth Hiemstra · 99039abe · 4c145905 · 4c145905 · 4c145905
Commit 4c145905 authored 9 years ago by Kenneth Hiemstra
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -2,8 +2,7 @@ hdl_lib_name = unb2_test_all
 hdl_library_clause_name = unb2_test_all_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
-hdl_lib_excludes = ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_1600 ip_arria10_phy_10gbase_r ip_arria10_transceiver_reset_controller_1
-
+hdl_lib_excludes = ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_2000 ip_arria10_phy_10gbase_r ip_arria10_transceiver_reset_controller_1
 hdl_lib_technology = ip_arria10

 synth_files =

--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -12,6 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx
                   ip_arria10_transceiver_reset_controller_1
                   ip_arria10_transceiver_reset_controller_24
                   ip_arria10_ddr4_8g_2400
+                   ip_arria10_ddr4_4g_2000

 synth_files =
    unb2_test_ddr_MB_I.vhd

--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -12,6 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx
                   ip_arria10_transceiver_reset_controller_1
                   ip_arria10_transceiver_reset_controller_24
                   ip_arria10_ddr4_8g_2400
+                   ip_arria10_ddr4_4g_2000

 synth_files =
    unb2_test_ddr_MB_II.vhd

--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -12,7 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx
                   ip_arria10_transceiver_reset_controller_1
                   ip_arria10_transceiver_reset_controller_24
                   ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_1600
+                   ip_arria10_ddr4_4g_2000

 synth_files =
    unb2_test_ddr_MB_I_II.vhd