diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index b0486490e96130f429d63f3fa30b02838dfe559c..afb79d2f088474b413b82e72220a957fee372bdf 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -2,8 +2,7 @@ hdl_lib_name = unb2_test_all
 hdl_library_clause_name = unb2_test_all_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
-hdl_lib_excludes = ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_1600 ip_arria10_phy_10gbase_r ip_arria10_transceiver_reset_controller_1
-
+hdl_lib_excludes = ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_2000 ip_arria10_phy_10gbase_r ip_arria10_transceiver_reset_controller_1
 hdl_lib_technology = ip_arria10
 
 synth_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 50e443058bfa9d244a3a69e030716d2787dadde0..b48fb0e7044e46b433a8197f7a2c39bcee7f13e8 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -12,6 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx
                    ip_arria10_transceiver_reset_controller_1
                    ip_arria10_transceiver_reset_controller_24
                    ip_arria10_ddr4_8g_2400
+                   ip_arria10_ddr4_4g_2000
 
 synth_files =
     unb2_test_ddr_MB_I.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index 61a5e209d190dba451cc297a08e576849cbd7783..a097f6e1c5385b6d99dfc8166f68f4c497346b3f 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -12,6 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx
                    ip_arria10_transceiver_reset_controller_1
                    ip_arria10_transceiver_reset_controller_24
                    ip_arria10_ddr4_8g_2400
+                   ip_arria10_ddr4_4g_2000
 
 synth_files =
     unb2_test_ddr_MB_II.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 3c3c279cc25a7452be8131dc00d5f72f0a4dbdbc..2dfd41d41c44244c74b3df29f01f78ad018e2d29 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -12,7 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx
                    ip_arria10_transceiver_reset_controller_1
                    ip_arria10_transceiver_reset_controller_24
                    ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_1600
+                   ip_arria10_ddr4_4g_2000
 
 synth_files =
     unb2_test_ddr_MB_I_II.vhd