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Commit 4b554803 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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add _e3sge3 option (for unb2a) to technology wrapper

parent dab2b871
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...@@ -60,4 +60,16 @@ BEGIN ...@@ -60,4 +60,16 @@ BEGIN
); );
END GENERATE; END GENERATE;
gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
u0 : ip_arria10_e3sge3_pll_clk125
PORT MAP (
rst => areset,
refclk => inclk0,
outclk_0 => c0,
outclk_1 => c1,
outclk_2 => c2,
outclk_3 => c3,
locked => locked
);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
...@@ -68,4 +68,16 @@ BEGIN ...@@ -68,4 +68,16 @@ BEGIN
); );
END GENERATE; END GENERATE;
gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
u0 : ip_arria10_e3sge3_pll_clk200
PORT MAP (
rst => areset,
refclk => inclk0,
outclk_0 => c0,
outclk_1 => c1,
outclk_2 => c2,
locked => locked
);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
...@@ -61,6 +61,19 @@ BEGIN ...@@ -61,6 +61,19 @@ BEGIN
); );
END GENERATE; END GENERATE;
gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
u0 : ip_arria10_e3sge3_pll_clk25
PORT MAP (
rst => areset,
refclk => inclk0,
outclk_0 => c0,
outclk_1 => c1,
outclk_2 => c2,
outclk_3 => c3,
locked => locked
);
END GENERATE;
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ip_stratixiv_pll_clk25 u0 : ip_stratixiv_pll_clk25
PORT MAP ( PORT MAP (
......
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