diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index 93332102c8fe5f09c27094f7f046cbdf5e6e95aa..d322fb59736cc719aecec2cfd6fb55f547ccadb3 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -60,4 +60,16 @@ BEGIN
     );
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_pll_clk125
+    PORT MAP (
+      rst      => areset, 
+      refclk   => inclk0, 
+      outclk_0 => c0, 
+      outclk_1 => c1, 
+      outclk_2 => c2, 
+      outclk_3 => c3, 
+      locked   => locked
+    );
+  END GENERATE;
 END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index b6b4a75789069e34a8ee6308c7c17201c68a09e5..1ad91b9f48af0f5a1722b8ce5332b45be362fc1b 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -68,4 +68,16 @@ BEGIN
     );
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_pll_clk200
+    PORT MAP (
+      rst      => areset, 
+      refclk   => inclk0, 
+      outclk_0 => c0, 
+      outclk_1 => c1, 
+      outclk_2 => c2, 
+      locked   => locked
+    );
+  END GENERATE;
+
 END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 1b77fd252f3120a1ea9216386b4af553251614b5..40e666e4a5211c882fb4b44bee02b8b34c886a92 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -61,6 +61,19 @@ BEGIN
     );
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_pll_clk25
+    PORT MAP (
+      rst      => areset, 
+      refclk   => inclk0, 
+      outclk_0 => c0, 
+      outclk_1 => c1, 
+      outclk_2 => c2, 
+      outclk_3 => c3, 
+      locked   => locked
+    );
+  END GENERATE;
+
   gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
     u0 : ip_stratixiv_pll_clk25
     PORT MAP (