From 4b554803fbef74e697d4baea3e398a7a2f26f382 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Tue, 19 Jan 2016 14:41:46 +0000
Subject: [PATCH] add _e3sge3 option (for unb2a) to technology wrapper
---
libraries/technology/pll/tech_pll_clk125.vhd | 12 ++++++++++++
libraries/technology/pll/tech_pll_clk200.vhd | 12 ++++++++++++
libraries/technology/pll/tech_pll_clk25.vhd | 13 +++++++++++++
3 files changed, 37 insertions(+)
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index 93332102c8..d322fb5973 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -60,4 +60,16 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_pll_clk125
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index b6b4a75789..1ad91b9f48 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -68,4 +68,16 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_pll_clk200
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ locked => locked
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 1b77fd252f..40e666e4a5 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -61,6 +61,19 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_pll_clk25
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
+
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ip_stratixiv_pll_clk25
PORT MAP (
--
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