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Commit 4b29777a authored by Eric Kooistra's avatar Eric Kooistra
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Corrected using wait between tb_end and sim stop using severity failure in...

Corrected using wait between tb_end and sim stop using severity failure in proc_common_stop_simulation().
parent 3bb2709e
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...@@ -534,6 +534,10 @@ PACKAGE BODY tb_common_pkg IS ...@@ -534,6 +534,10 @@ PACKAGE BODY tb_common_pkg IS
-- Stop the simulation or only report NOTE -- Stop the simulation or only report NOTE
tb_end <= '1'; tb_end <= '1';
-- For modelsim_regression_test_vhdl.py:
-- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
-- stop the simulation using failure, without causing the test to fail.
WAIT FOR 1 ns;
IF g_tb_end=FALSE THEN IF g_tb_end=FALSE THEN
REPORT "Tb Simulation finished." SEVERITY NOTE; REPORT "Tb Simulation finished." SEVERITY NOTE;
ELSE ELSE
......
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