diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index a5c611fc922da8b583a05ec911a6c3c2f3efbc25..cab5db0eeac5b788e51baecfe0e5cd65ea523734 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -534,6 +534,10 @@ PACKAGE BODY tb_common_pkg IS
     
     -- Stop the simulation or only report NOTE
     tb_end <= '1';
+    -- For modelsim_regression_test_vhdl.py:
+    -- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
+    -- stop the simulation using failure, without causing the test to fail.
+    WAIT FOR 1 ns;
     IF g_tb_end=FALSE THEN
       REPORT "Tb Simulation finished." SEVERITY NOTE;
     ELSE