From 4b29777abe7a39ae0ef746fa39ac5ec23ec4ae7a Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 12 Jun 2018 06:20:48 +0000
Subject: [PATCH] Corrected using wait between tb_end and sim stop using
severity failure in proc_common_stop_simulation().
---
libraries/base/common/tb/vhdl/tb_common_pkg.vhd | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index a5c611fc92..cab5db0eea 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -534,6 +534,10 @@ PACKAGE BODY tb_common_pkg IS
-- Stop the simulation or only report NOTE
tb_end <= '1';
+ -- For modelsim_regression_test_vhdl.py:
+ -- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
+ -- stop the simulation using failure, without causing the test to fail.
+ WAIT FOR 1 ns;
IF g_tb_end=FALSE THEN
REPORT "Tb Simulation finished." SEVERITY NOTE;
ELSE
--
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