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Commit 47f0f4f0 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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tie together the transceiver IP for Arria 10

parent 4feea4dc
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......@@ -96,7 +96,7 @@ architecture str of tech_transceiver_arria10_48 is
rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X');
rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
);
end component transceiver_reset_controller;
end component transceiver_reset_controller_48;
component transceiver_pll is
port (
......@@ -191,4 +191,4 @@ begin
tx_serial_clk <= (others => mcgb_serial_clk);
txpll_cal_busy <= tx_cal_busy when pll_cal_busy = '0' else (others => '1');
end;
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