From 47f0f4f0062178be74a12083dc4ea85077498772 Mon Sep 17 00:00:00 2001 From: Jonathan Hargreaves <hargreaves@astron.nl> Date: Wed, 1 Oct 2014 13:40:42 +0000 Subject: [PATCH] tie together the transceiver IP for Arria 10 --- .../technology/transceiver/tech_transceiver_arria10_48.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd b/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd index 600accd5dc..d68cc81f1c 100644 --- a/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd +++ b/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd @@ -96,7 +96,7 @@ architecture str of tech_transceiver_arria10_48 is rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy ); - end component transceiver_reset_controller; + end component transceiver_reset_controller_48; component transceiver_pll is port ( @@ -191,4 +191,4 @@ begin tx_serial_clk <= (others => mcgb_serial_clk); txpll_cal_busy <= tx_cal_busy when pll_cal_busy = '0' else (others => '1'); - +end; -- GitLab