-Added MM master generation;

-All compiles OK in modelsim (excl. non-existing TB)!

applications/arts/designs/arts_unb1_sc1/src/arts_unb1_sc1_offload.py

@@ -12,7 +12,7 @@ VHDL_INST = """  u_arts_unb1_sc1_offload : ENTITY work.arts_unb1_sc1_offload
     snk_out => arts_unb1_sc1_offload_snk_out,
 
     src_out => arts_unb1_sc1_offload_src_out,
-    src_in  => arts_unb1_sc1_offload_src_i,
+    src_in  => arts_unb1_sc1_offload_src_in,
 
     ID      => ID
   );

applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd

@@ -247,7 +247,7 @@ BEGIN
     snk_out => arts_unb1_sc1_offload_snk_out,
 
     src_out => arts_unb1_sc1_offload_src_out,
-    src_in  => arts_unb1_sc1_offload_src_i,
+    src_in  => arts_unb1_sc1_offload_src_in,
 
     ID      => ID
   );
@@ -353,6 +353,8 @@ BEGIN
   PORT MAP(  
     mm_rst                   => mm_rst,
     mm_clk                   => mm_clk,
+    eth1g_mm_rst             => eth1g_mm_rst,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
     pout_wdi                 => pout_wdi,
     bf_unit_ram_ss_ss_wide_mosi =>  bf_unit_ram_ss_ss_wide_mosi,
     bf_unit_ram_ss_ss_wide_miso =>  bf_unit_ram_ss_ss_wide_miso,
@@ -361,7 +363,27 @@ BEGIN
     bf_unit_ram_st_sst_mosi =>  bf_unit_ram_st_sst_mosi,
     bf_unit_ram_st_sst_miso =>  bf_unit_ram_st_sst_miso,
     bf_unit_reg_st_sst_mosi =>  bf_unit_reg_st_sst_mosi,
-    bf_unit_reg_st_sst_miso =>  bf_unit_reg_st_sst_miso
+    bf_unit_reg_st_sst_miso =>  bf_unit_reg_st_sst_miso,
+    eth1g_tse_mosi =>  eth1g_tse_mosi,
+    eth1g_tse_miso =>  eth1g_tse_miso,
+    eth1g_reg_mosi =>  eth1g_reg_mosi,
+    eth1g_reg_miso =>  eth1g_reg_miso,
+    eth1g_ram_mosi =>  eth1g_ram_mosi,
+    eth1g_ram_miso =>  eth1g_ram_miso,
+    reg_unb_sens_mosi =>  reg_unb_sens_mosi,
+    reg_unb_sens_miso =>  reg_unb_sens_miso,
+    reg_epcs_mosi =>  reg_epcs_mosi,
+    reg_epcs_miso =>  reg_epcs_miso,
+    reg_remu_mosi =>  reg_remu_mosi,
+    reg_remu_miso =>  reg_remu_miso,
+    reg_ppsh_mosi =>  reg_ppsh_mosi,
+    reg_ppsh_miso =>  reg_ppsh_miso,
+    reg_unb_system_info_mosi =>  reg_unb_system_info_mosi,
+    reg_unb_system_info_miso =>  reg_unb_system_info_miso,
+    rom_unb_system_info_mosi =>  rom_unb_system_info_mosi,
+    rom_unb_system_info_miso =>  rom_unb_system_info_miso,
+    reg_wdi_mosi =>  reg_wdi_mosi,
+    reg_wdi_miso =>  reg_wdi_miso
   );
 
 END str;

applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg

@@ -3,11 +3,11 @@ hdl_library_clause_name = arts_unb1_sc1_bg_single_pol_lib
 hdl_lib_uses_synth = common dp mm diag bf unb1_board 
 hdl_lib_technology = ip_stratixiv
 synth_files =
-    arts_unb1_sc1_offload.vhd
-    generated/mm_master.vhd
-    generated/arts_unb1_sc1_bg_single_pol.vhd
+    ../arts_unb1_sc1_offload.vhd
+    ../generated/mm_master.vhd
+    ../generated/arts_unb1_sc1_bg_single_pol.vhd
 test_bench_files =
-    generated/tb_arts_unb1_sc1_bg_single_pol.vhd
+    tb_arts_unb1_sc1_bg_single_pol.vhd
 quartus_copy_files =
     qsys_mm_master.qsys .
 quartus_qsf_files =

applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE; -- So we can use STD_LOGIC etc.
+    USE IEEE.STD_LOGIC_1164.ALL;
+    USE IEEE.NUMERIC_STD.ALL;
+LIBRARY common_lib; -- Funcions such as sel_a_b()
+    USE common_lib.common_pkg.ALL;
+    USE common_lib.common_mem_pkg.ALL;
+LIBRARY dp_lib;
+    USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY mm_master IS
+  GENERIC (
+    g_sim         : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0
+  );
+  PORT (
+    mm_rst                   : IN  STD_LOGIC;
+    mm_clk                   : IN  STD_LOGIC;
+    eth1g_mm_rst             : OUT STD_LOGIC;
+    eth1g_reg_interrupt      : IN  STD_LOGIC;
+    pout_wdi                 : OUT STD_LOGIC;
+    bf_unit_ram_ss_ss_wide_mosi : OUT t_mem_mosi;
+    bf_unit_ram_ss_ss_wide_miso : IN  t_mem_miso;
+    bf_unit_ram_bf_weights_mosi : OUT t_mem_mosi;
+    bf_unit_ram_bf_weights_miso : IN  t_mem_miso;
+    bf_unit_ram_st_sst_mosi : OUT t_mem_mosi;
+    bf_unit_ram_st_sst_miso : IN  t_mem_miso;
+    bf_unit_reg_st_sst_mosi : OUT t_mem_mosi;
+    bf_unit_reg_st_sst_miso : IN  t_mem_miso;
+    eth1g_tse_mosi : OUT t_mem_mosi;
+    eth1g_tse_miso : IN  t_mem_miso;
+    eth1g_reg_mosi : OUT t_mem_mosi;
+    eth1g_reg_miso : IN  t_mem_miso;
+    eth1g_ram_mosi : OUT t_mem_mosi;
+    eth1g_ram_miso : IN  t_mem_miso;
+    reg_unb_sens_mosi : OUT t_mem_mosi;
+    reg_unb_sens_miso : IN  t_mem_miso;
+    reg_epcs_mosi : OUT t_mem_mosi;
+    reg_epcs_miso : IN  t_mem_miso;
+    reg_remu_mosi : OUT t_mem_mosi;
+    reg_remu_miso : IN  t_mem_miso;
+    reg_ppsh_mosi : OUT t_mem_mosi;
+    reg_ppsh_miso : IN  t_mem_miso;
+    reg_unb_system_info_mosi : OUT t_mem_mosi;
+    reg_unb_system_info_miso : IN  t_mem_miso;
+    rom_unb_system_info_mosi : OUT t_mem_mosi;
+    rom_unb_system_info_miso : IN  t_mem_miso;
+    reg_wdi_mosi : OUT t_mem_mosi;
+    reg_wdi_miso : IN  t_mem_miso
+  );
+END mm_master;
+ARCHITECTURE str OF mm_master IS
+
+
+  COMPONENT QSYS_MM_MASTER IS
+    PORT (
+      clk_0                       : IN STD_LOGIC;
+      reset_n                     : IN STD_LOGIC;
+
+      eth1g_mm_rst                : OUT STD_LOGIC;
+      eth1g_irq                   : IN STD_LOGIC;
+      out_port_from_the_pio_wdi   : OUT STD_LOGIC;
+
+      bf_unit_ram_ss_ss_wide_address_export    : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
+      bf_unit_ram_ss_ss_wide_clk_export        : OUT STD_LOGIC;
+      bf_unit_ram_ss_ss_wide_read_export       : OUT STD_LOGIC;
+      bf_unit_ram_ss_ss_wide_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      bf_unit_ram_ss_ss_wide_reset_export      : OUT STD_LOGIC;
+      bf_unit_ram_ss_ss_wide_write_export      : OUT STD_LOGIC;
+      bf_unit_ram_ss_ss_wide_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      bf_unit_ram_bf_weights_address_export    : OUT STD_LOGIC_VECTOR(5-1 DOWNTO 0);
+      bf_unit_ram_bf_weights_clk_export        : OUT STD_LOGIC;
+      bf_unit_ram_bf_weights_read_export       : OUT STD_LOGIC;
+      bf_unit_ram_bf_weights_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      bf_unit_ram_bf_weights_reset_export      : OUT STD_LOGIC;
+      bf_unit_ram_bf_weights_write_export      : OUT STD_LOGIC;
+      bf_unit_ram_bf_weights_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      bf_unit_ram_st_sst_address_export    : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+      bf_unit_ram_st_sst_clk_export        : OUT STD_LOGIC;
+      bf_unit_ram_st_sst_read_export       : OUT STD_LOGIC;
+      bf_unit_ram_st_sst_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      bf_unit_ram_st_sst_reset_export      : OUT STD_LOGIC;
+      bf_unit_ram_st_sst_write_export      : OUT STD_LOGIC;
+      bf_unit_ram_st_sst_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      bf_unit_reg_st_sst_address_export    : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0);
+      bf_unit_reg_st_sst_clk_export        : OUT STD_LOGIC;
+      bf_unit_reg_st_sst_read_export       : OUT STD_LOGIC;
+      bf_unit_reg_st_sst_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      bf_unit_reg_st_sst_reset_export      : OUT STD_LOGIC;
+      bf_unit_reg_st_sst_write_export      : OUT STD_LOGIC;
+      bf_unit_reg_st_sst_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      eth1g_tse_address_export    : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+      eth1g_tse_clk_export        : OUT STD_LOGIC;
+      eth1g_tse_read_export       : OUT STD_LOGIC;
+      eth1g_tse_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      eth1g_tse_reset_export      : OUT STD_LOGIC;
+      eth1g_tse_write_export      : OUT STD_LOGIC;
+      eth1g_tse_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      eth1g_tse_waitrequest : IN STD_LOGIC;
+
+      eth1g_reg_address_export    : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
+      eth1g_reg_clk_export        : OUT STD_LOGIC;
+      eth1g_reg_read_export       : OUT STD_LOGIC;
+      eth1g_reg_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      eth1g_reg_reset_export      : OUT STD_LOGIC;
+      eth1g_reg_write_export      : OUT STD_LOGIC;
+      eth1g_reg_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      eth1g_ram_address_export    : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+      eth1g_ram_clk_export        : OUT STD_LOGIC;
+      eth1g_ram_read_export       : OUT STD_LOGIC;
+      eth1g_ram_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      eth1g_ram_reset_export      : OUT STD_LOGIC;
+      eth1g_ram_write_export      : OUT STD_LOGIC;
+      eth1g_ram_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      reg_unb_sens_address_export    : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+      reg_unb_sens_clk_export        : OUT STD_LOGIC;
+      reg_unb_sens_read_export       : OUT STD_LOGIC;
+      reg_unb_sens_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      reg_unb_sens_reset_export      : OUT STD_LOGIC;
+      reg_unb_sens_write_export      : OUT STD_LOGIC;
+      reg_unb_sens_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      reg_epcs_address_export    : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+      reg_epcs_clk_export        : OUT STD_LOGIC;
+      reg_epcs_read_export       : OUT STD_LOGIC;
+      reg_epcs_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      reg_epcs_reset_export      : OUT STD_LOGIC;
+      reg_epcs_write_export      : OUT STD_LOGIC;
+      reg_epcs_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      reg_remu_address_export    : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+      reg_remu_clk_export        : OUT STD_LOGIC;
+      reg_remu_read_export       : OUT STD_LOGIC;
+      reg_remu_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      reg_remu_reset_export      : OUT STD_LOGIC;
+      reg_remu_write_export      : OUT STD_LOGIC;
+      reg_remu_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      reg_ppsh_address_export    : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
+      reg_ppsh_clk_export        : OUT STD_LOGIC;
+      reg_ppsh_read_export       : OUT STD_LOGIC;
+      reg_ppsh_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      reg_ppsh_reset_export      : OUT STD_LOGIC;
+      reg_ppsh_write_export      : OUT STD_LOGIC;
+      reg_ppsh_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      reg_unb_system_info_address_export    : OUT STD_LOGIC_VECTOR(5-1 DOWNTO 0);
+      reg_unb_system_info_clk_export        : OUT STD_LOGIC;
+      reg_unb_system_info_read_export       : OUT STD_LOGIC;
+      reg_unb_system_info_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      reg_unb_system_info_reset_export      : OUT STD_LOGIC;
+      reg_unb_system_info_write_export      : OUT STD_LOGIC;
+      reg_unb_system_info_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      rom_unb_system_info_address_export    : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+      rom_unb_system_info_clk_export        : OUT STD_LOGIC;
+      rom_unb_system_info_read_export       : OUT STD_LOGIC;
+      rom_unb_system_info_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      rom_unb_system_info_reset_export      : OUT STD_LOGIC;
+      rom_unb_system_info_write_export      : OUT STD_LOGIC;
+      rom_unb_system_info_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+      reg_wdi_address_export    : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
+      reg_wdi_clk_export        : OUT STD_LOGIC;
+      reg_wdi_read_export       : OUT STD_LOGIC;
+      reg_wdi_readdata_export   : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+      reg_wdi_reset_export      : OUT STD_LOGIC;
+      reg_wdi_write_export      : OUT STD_LOGIC;
+      reg_wdi_writedata_export  : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
+        );
+    END COMPONENT QSYS_MM_MASTER;
+  SIGNAL mm_rst_n : STD_LOGIC;
+BEGIN
+
+  mm_rst_n <= NOT mm_rst;
+
+  gen_qsys_mm_master : IF g_sim = FALSE GENERATE
+    u_qsys_mm_master : qsys_mm_master
+    PORT MAP (
+      clk_0                                         => mm_clk,
+      reset_n                                       => mm_rst_n,
+
+      eth1g_mm_rst                                  => eth1g_mm_rst,
+      eth1g_irq                                     => eth1g_reg_interrupt,
+      out_port_from_the_pio_wdi                     => pout_wdi,
+
+      bf_unit_ram_ss_ss_wide_address_export    => bf_unit_ram_ss_ss_wide_mosi.address(4-1 DOWNTO 0),
+      bf_unit_ram_ss_ss_wide_clk_export        => OPEN,
+      bf_unit_ram_ss_ss_wide_read_export       => bf_unit_ram_ss_ss_wide_mosi.rd,
+      bf_unit_ram_ss_ss_wide_readdata_export   => bf_unit_ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
+      bf_unit_ram_ss_ss_wide_reset_export      => OPEN,
+      bf_unit_ram_ss_ss_wide_write_export      => bf_unit_ram_ss_ss_wide_mosi.wr,
+      bf_unit_ram_ss_ss_wide_writedata_export  => bf_unit_ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      bf_unit_ram_bf_weights_address_export    => bf_unit_ram_bf_weights_mosi.address(5-1 DOWNTO 0),
+      bf_unit_ram_bf_weights_clk_export        => OPEN,
+      bf_unit_ram_bf_weights_read_export       => bf_unit_ram_bf_weights_mosi.rd,
+      bf_unit_ram_bf_weights_readdata_export   => bf_unit_ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
+      bf_unit_ram_bf_weights_reset_export      => OPEN,
+      bf_unit_ram_bf_weights_write_export      => bf_unit_ram_bf_weights_mosi.wr,
+      bf_unit_ram_bf_weights_writedata_export  => bf_unit_ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      bf_unit_ram_st_sst_address_export    => bf_unit_ram_st_sst_mosi.address(3-1 DOWNTO 0),
+      bf_unit_ram_st_sst_clk_export        => OPEN,
+      bf_unit_ram_st_sst_read_export       => bf_unit_ram_st_sst_mosi.rd,
+      bf_unit_ram_st_sst_readdata_export   => bf_unit_ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+      bf_unit_ram_st_sst_reset_export      => OPEN,
+      bf_unit_ram_st_sst_write_export      => bf_unit_ram_st_sst_mosi.wr,
+      bf_unit_ram_st_sst_writedata_export  => bf_unit_ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      bf_unit_reg_st_sst_address_export    => bf_unit_reg_st_sst_mosi.address(6-1 DOWNTO 0),
+      bf_unit_reg_st_sst_clk_export        => OPEN,
+      bf_unit_reg_st_sst_read_export       => bf_unit_reg_st_sst_mosi.rd,
+      bf_unit_reg_st_sst_readdata_export   => bf_unit_reg_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+      bf_unit_reg_st_sst_reset_export      => OPEN,
+      bf_unit_reg_st_sst_write_export      => bf_unit_reg_st_sst_mosi.wr,
+      bf_unit_reg_st_sst_writedata_export  => bf_unit_reg_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      eth1g_tse_address_export    => eth1g_tse_mosi.address(10-1 DOWNTO 0),
+      eth1g_tse_clk_export        => OPEN,
+      eth1g_tse_read_export       => eth1g_tse_mosi.rd,
+      eth1g_tse_readdata_export   => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+      eth1g_tse_reset_export      => OPEN,
+      eth1g_tse_write_export      => eth1g_tse_mosi.wr,
+      eth1g_tse_writedata_export  => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      eth1g_tse_waitrequest => eth1g_tse_miso.waitrequest,
+
+      eth1g_reg_address_export    => eth1g_reg_mosi.address(4-1 DOWNTO 0),
+      eth1g_reg_clk_export        => OPEN,
+      eth1g_reg_read_export       => eth1g_reg_mosi.rd,
+      eth1g_reg_readdata_export   => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+      eth1g_reg_reset_export      => OPEN,
+      eth1g_reg_write_export      => eth1g_reg_mosi.wr,
+      eth1g_reg_writedata_export  => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      eth1g_ram_address_export    => eth1g_ram_mosi.address(10-1 DOWNTO 0),
+      eth1g_ram_clk_export        => OPEN,
+      eth1g_ram_read_export       => eth1g_ram_mosi.rd,
+      eth1g_ram_readdata_export   => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+      eth1g_ram_reset_export      => OPEN,
+      eth1g_ram_write_export      => eth1g_ram_mosi.wr,
+      eth1g_ram_writedata_export  => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_unb_sens_address_export    => reg_unb_sens_mosi.address(3-1 DOWNTO 0),
+      reg_unb_sens_clk_export        => OPEN,
+      reg_unb_sens_read_export       => reg_unb_sens_mosi.rd,
+      reg_unb_sens_readdata_export   => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_unb_sens_reset_export      => OPEN,
+      reg_unb_sens_write_export      => reg_unb_sens_mosi.wr,
+      reg_unb_sens_writedata_export  => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_epcs_address_export    => reg_epcs_mosi.address(3-1 DOWNTO 0),
+      reg_epcs_clk_export        => OPEN,
+      reg_epcs_read_export       => reg_epcs_mosi.rd,
+      reg_epcs_readdata_export   => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_epcs_reset_export      => OPEN,
+      reg_epcs_write_export      => reg_epcs_mosi.wr,
+      reg_epcs_writedata_export  => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_remu_address_export    => reg_remu_mosi.address(3-1 DOWNTO 0),
+      reg_remu_clk_export        => OPEN,
+      reg_remu_read_export       => reg_remu_mosi.rd,
+      reg_remu_readdata_export   => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_remu_reset_export      => OPEN,
+      reg_remu_write_export      => reg_remu_mosi.wr,
+      reg_remu_writedata_export  => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_ppsh_address_export    => reg_ppsh_mosi.address(1-1 DOWNTO 0),
+      reg_ppsh_clk_export        => OPEN,
+      reg_ppsh_read_export       => reg_ppsh_mosi.rd,
+      reg_ppsh_readdata_export   => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_ppsh_reset_export      => OPEN,
+      reg_ppsh_write_export      => reg_ppsh_mosi.wr,
+      reg_ppsh_writedata_export  => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_unb_system_info_address_export    => reg_unb_system_info_mosi.address(5-1 DOWNTO 0),
+      reg_unb_system_info_clk_export        => OPEN,
+      reg_unb_system_info_read_export       => reg_unb_system_info_mosi.rd,
+      reg_unb_system_info_readdata_export   => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_unb_system_info_reset_export      => OPEN,
+      reg_unb_system_info_write_export      => reg_unb_system_info_mosi.wr,
+      reg_unb_system_info_writedata_export  => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      rom_unb_system_info_address_export    => rom_unb_system_info_mosi.address(10-1 DOWNTO 0),
+      rom_unb_system_info_clk_export        => OPEN,
+      rom_unb_system_info_read_export       => rom_unb_system_info_mosi.rd,
+      rom_unb_system_info_readdata_export   => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+      rom_unb_system_info_reset_export      => OPEN,
+      rom_unb_system_info_write_export      => rom_unb_system_info_mosi.wr,
+      rom_unb_system_info_writedata_export  => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_wdi_address_export    => reg_wdi_mosi.address(1-1 DOWNTO 0),
+      reg_wdi_clk_export        => OPEN,
+      reg_wdi_read_export       => reg_wdi_mosi.rd,
+      reg_wdi_readdata_export   => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_wdi_reset_export      => OPEN,
+      reg_wdi_write_export      => reg_wdi_mosi.wr,
+      reg_wdi_writedata_export  => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
+      );
+  END GENERATE;
+
+
+END str;