diff --git a/applications/arts/designs/arts_unb1_sc1/src/arts_unb1_sc1_offload.py b/applications/arts/designs/arts_unb1_sc1/src/arts_unb1_sc1_offload.py
index 6032dc2cf4d6af3ca19ce9c24f0f0c35699203cb..bd981111d73a965e75b66acac569f7b94b48185e 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/arts_unb1_sc1_offload.py
+++ b/applications/arts/designs/arts_unb1_sc1/src/arts_unb1_sc1_offload.py
@@ -12,7 +12,7 @@ VHDL_INST = """ u_arts_unb1_sc1_offload : ENTITY work.arts_unb1_sc1_offload
snk_out => arts_unb1_sc1_offload_snk_out,
src_out => arts_unb1_sc1_offload_src_out,
- src_in => arts_unb1_sc1_offload_src_i,
+ src_in => arts_unb1_sc1_offload_src_in,
ID => ID
);
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd b/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
index ccb7810e59a5d0fae5bf1a31601896d78a075db0..60bb845baf348fbeefcb0704998ac2a64bd5a70c 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
@@ -247,7 +247,7 @@ BEGIN
snk_out => arts_unb1_sc1_offload_snk_out,
src_out => arts_unb1_sc1_offload_src_out,
- src_in => arts_unb1_sc1_offload_src_i,
+ src_in => arts_unb1_sc1_offload_src_in,
ID => ID
);
@@ -353,6 +353,8 @@ BEGIN
PORT MAP(
mm_rst => mm_rst,
mm_clk => mm_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
pout_wdi => pout_wdi,
bf_unit_ram_ss_ss_wide_mosi => bf_unit_ram_ss_ss_wide_mosi,
bf_unit_ram_ss_ss_wide_miso => bf_unit_ram_ss_ss_wide_miso,
@@ -361,7 +363,27 @@ BEGIN
bf_unit_ram_st_sst_mosi => bf_unit_ram_st_sst_mosi,
bf_unit_ram_st_sst_miso => bf_unit_ram_st_sst_miso,
bf_unit_reg_st_sst_mosi => bf_unit_reg_st_sst_mosi,
- bf_unit_reg_st_sst_miso => bf_unit_reg_st_sst_miso
+ bf_unit_reg_st_sst_miso => bf_unit_reg_st_sst_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso
);
END str;
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
index f31268d328492ef66b5ae2b4cfffe5b3947aa24f..13b21548415ff4ae64c82f1e5ad2d6029cd15f24 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
@@ -3,11 +3,11 @@ hdl_library_clause_name = arts_unb1_sc1_bg_single_pol_lib
hdl_lib_uses_synth = common dp mm diag bf unb1_board
hdl_lib_technology = ip_stratixiv
synth_files =
- arts_unb1_sc1_offload.vhd
- generated/mm_master.vhd
- generated/arts_unb1_sc1_bg_single_pol.vhd
+ ../arts_unb1_sc1_offload.vhd
+ ../generated/mm_master.vhd
+ ../generated/arts_unb1_sc1_bg_single_pol.vhd
test_bench_files =
- generated/tb_arts_unb1_sc1_bg_single_pol.vhd
+ tb_arts_unb1_sc1_bg_single_pol.vhd
quartus_copy_files =
qsys_mm_master.qsys .
quartus_qsf_files =
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd b/applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed864d7b3b35fbf45771f7cd73680e7d326671e9
--- /dev/null
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd
@@ -0,0 +1,334 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE; -- So we can use STD_LOGIC etc.
+ USE IEEE.STD_LOGIC_1164.ALL;
+ USE IEEE.NUMERIC_STD.ALL;
+LIBRARY common_lib; -- Funcions such as sel_a_b()
+ USE common_lib.common_pkg.ALL;
+ USE common_lib.common_mem_pkg.ALL;
+LIBRARY dp_lib;
+ USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY mm_master IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ pout_wdi : OUT STD_LOGIC;
+ bf_unit_ram_ss_ss_wide_mosi : OUT t_mem_mosi;
+ bf_unit_ram_ss_ss_wide_miso : IN t_mem_miso;
+ bf_unit_ram_bf_weights_mosi : OUT t_mem_mosi;
+ bf_unit_ram_bf_weights_miso : IN t_mem_miso;
+ bf_unit_ram_st_sst_mosi : OUT t_mem_mosi;
+ bf_unit_ram_st_sst_miso : IN t_mem_miso;
+ bf_unit_reg_st_sst_mosi : OUT t_mem_mosi;
+ bf_unit_reg_st_sst_miso : IN t_mem_miso;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso;
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso;
+ reg_epcs_mosi : OUT t_mem_mosi;
+ reg_epcs_miso : IN t_mem_miso;
+ reg_remu_mosi : OUT t_mem_mosi;
+ reg_remu_miso : IN t_mem_miso;
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso;
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso;
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso
+ );
+END mm_master;
+ARCHITECTURE str OF mm_master IS
+
+
+ COMPONENT QSYS_MM_MASTER IS
+ PORT (
+ clk_0 : IN STD_LOGIC;
+ reset_n : IN STD_LOGIC;
+
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_irq : IN STD_LOGIC;
+ out_port_from_the_pio_wdi : OUT STD_LOGIC;
+
+ bf_unit_ram_ss_ss_wide_address_export : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
+ bf_unit_ram_ss_ss_wide_clk_export : OUT STD_LOGIC;
+ bf_unit_ram_ss_ss_wide_read_export : OUT STD_LOGIC;
+ bf_unit_ram_ss_ss_wide_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ bf_unit_ram_ss_ss_wide_reset_export : OUT STD_LOGIC;
+ bf_unit_ram_ss_ss_wide_write_export : OUT STD_LOGIC;
+ bf_unit_ram_ss_ss_wide_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ bf_unit_ram_bf_weights_address_export : OUT STD_LOGIC_VECTOR(5-1 DOWNTO 0);
+ bf_unit_ram_bf_weights_clk_export : OUT STD_LOGIC;
+ bf_unit_ram_bf_weights_read_export : OUT STD_LOGIC;
+ bf_unit_ram_bf_weights_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ bf_unit_ram_bf_weights_reset_export : OUT STD_LOGIC;
+ bf_unit_ram_bf_weights_write_export : OUT STD_LOGIC;
+ bf_unit_ram_bf_weights_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ bf_unit_ram_st_sst_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+ bf_unit_ram_st_sst_clk_export : OUT STD_LOGIC;
+ bf_unit_ram_st_sst_read_export : OUT STD_LOGIC;
+ bf_unit_ram_st_sst_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ bf_unit_ram_st_sst_reset_export : OUT STD_LOGIC;
+ bf_unit_ram_st_sst_write_export : OUT STD_LOGIC;
+ bf_unit_ram_st_sst_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ bf_unit_reg_st_sst_address_export : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0);
+ bf_unit_reg_st_sst_clk_export : OUT STD_LOGIC;
+ bf_unit_reg_st_sst_read_export : OUT STD_LOGIC;
+ bf_unit_reg_st_sst_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ bf_unit_reg_st_sst_reset_export : OUT STD_LOGIC;
+ bf_unit_reg_st_sst_write_export : OUT STD_LOGIC;
+ bf_unit_reg_st_sst_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ eth1g_tse_address_export : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+ eth1g_tse_clk_export : OUT STD_LOGIC;
+ eth1g_tse_read_export : OUT STD_LOGIC;
+ eth1g_tse_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ eth1g_tse_reset_export : OUT STD_LOGIC;
+ eth1g_tse_write_export : OUT STD_LOGIC;
+ eth1g_tse_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ eth1g_tse_waitrequest : IN STD_LOGIC;
+
+ eth1g_reg_address_export : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
+ eth1g_reg_clk_export : OUT STD_LOGIC;
+ eth1g_reg_read_export : OUT STD_LOGIC;
+ eth1g_reg_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ eth1g_reg_reset_export : OUT STD_LOGIC;
+ eth1g_reg_write_export : OUT STD_LOGIC;
+ eth1g_reg_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ eth1g_ram_address_export : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+ eth1g_ram_clk_export : OUT STD_LOGIC;
+ eth1g_ram_read_export : OUT STD_LOGIC;
+ eth1g_ram_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ eth1g_ram_reset_export : OUT STD_LOGIC;
+ eth1g_ram_write_export : OUT STD_LOGIC;
+ eth1g_ram_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ reg_unb_sens_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+ reg_unb_sens_clk_export : OUT STD_LOGIC;
+ reg_unb_sens_read_export : OUT STD_LOGIC;
+ reg_unb_sens_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ reg_unb_sens_reset_export : OUT STD_LOGIC;
+ reg_unb_sens_write_export : OUT STD_LOGIC;
+ reg_unb_sens_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ reg_epcs_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+ reg_epcs_clk_export : OUT STD_LOGIC;
+ reg_epcs_read_export : OUT STD_LOGIC;
+ reg_epcs_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ reg_epcs_reset_export : OUT STD_LOGIC;
+ reg_epcs_write_export : OUT STD_LOGIC;
+ reg_epcs_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ reg_remu_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
+ reg_remu_clk_export : OUT STD_LOGIC;
+ reg_remu_read_export : OUT STD_LOGIC;
+ reg_remu_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ reg_remu_reset_export : OUT STD_LOGIC;
+ reg_remu_write_export : OUT STD_LOGIC;
+ reg_remu_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ reg_ppsh_address_export : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
+ reg_ppsh_clk_export : OUT STD_LOGIC;
+ reg_ppsh_read_export : OUT STD_LOGIC;
+ reg_ppsh_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ reg_ppsh_reset_export : OUT STD_LOGIC;
+ reg_ppsh_write_export : OUT STD_LOGIC;
+ reg_ppsh_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ reg_unb_system_info_address_export : OUT STD_LOGIC_VECTOR(5-1 DOWNTO 0);
+ reg_unb_system_info_clk_export : OUT STD_LOGIC;
+ reg_unb_system_info_read_export : OUT STD_LOGIC;
+ reg_unb_system_info_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ reg_unb_system_info_reset_export : OUT STD_LOGIC;
+ reg_unb_system_info_write_export : OUT STD_LOGIC;
+ reg_unb_system_info_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ rom_unb_system_info_address_export : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
+ rom_unb_system_info_clk_export : OUT STD_LOGIC;
+ rom_unb_system_info_read_export : OUT STD_LOGIC;
+ rom_unb_system_info_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ rom_unb_system_info_reset_export : OUT STD_LOGIC;
+ rom_unb_system_info_write_export : OUT STD_LOGIC;
+ rom_unb_system_info_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ reg_wdi_address_export : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
+ reg_wdi_clk_export : OUT STD_LOGIC;
+ reg_wdi_read_export : OUT STD_LOGIC;
+ reg_wdi_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ reg_wdi_reset_export : OUT STD_LOGIC;
+ reg_wdi_write_export : OUT STD_LOGIC;
+ reg_wdi_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
+ );
+ END COMPONENT QSYS_MM_MASTER;
+ SIGNAL mm_rst_n : STD_LOGIC;
+BEGIN
+
+ mm_rst_n <= NOT mm_rst;
+
+ gen_qsys_mm_master : IF g_sim = FALSE GENERATE
+ u_qsys_mm_master : qsys_mm_master
+ PORT MAP (
+ clk_0 => mm_clk,
+ reset_n => mm_rst_n,
+
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_irq => eth1g_reg_interrupt,
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ bf_unit_ram_ss_ss_wide_address_export => bf_unit_ram_ss_ss_wide_mosi.address(4-1 DOWNTO 0),
+ bf_unit_ram_ss_ss_wide_clk_export => OPEN,
+ bf_unit_ram_ss_ss_wide_read_export => bf_unit_ram_ss_ss_wide_mosi.rd,
+ bf_unit_ram_ss_ss_wide_readdata_export => bf_unit_ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
+ bf_unit_ram_ss_ss_wide_reset_export => OPEN,
+ bf_unit_ram_ss_ss_wide_write_export => bf_unit_ram_ss_ss_wide_mosi.wr,
+ bf_unit_ram_ss_ss_wide_writedata_export => bf_unit_ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ bf_unit_ram_bf_weights_address_export => bf_unit_ram_bf_weights_mosi.address(5-1 DOWNTO 0),
+ bf_unit_ram_bf_weights_clk_export => OPEN,
+ bf_unit_ram_bf_weights_read_export => bf_unit_ram_bf_weights_mosi.rd,
+ bf_unit_ram_bf_weights_readdata_export => bf_unit_ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
+ bf_unit_ram_bf_weights_reset_export => OPEN,
+ bf_unit_ram_bf_weights_write_export => bf_unit_ram_bf_weights_mosi.wr,
+ bf_unit_ram_bf_weights_writedata_export => bf_unit_ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ bf_unit_ram_st_sst_address_export => bf_unit_ram_st_sst_mosi.address(3-1 DOWNTO 0),
+ bf_unit_ram_st_sst_clk_export => OPEN,
+ bf_unit_ram_st_sst_read_export => bf_unit_ram_st_sst_mosi.rd,
+ bf_unit_ram_st_sst_readdata_export => bf_unit_ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ bf_unit_ram_st_sst_reset_export => OPEN,
+ bf_unit_ram_st_sst_write_export => bf_unit_ram_st_sst_mosi.wr,
+ bf_unit_ram_st_sst_writedata_export => bf_unit_ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ bf_unit_reg_st_sst_address_export => bf_unit_reg_st_sst_mosi.address(6-1 DOWNTO 0),
+ bf_unit_reg_st_sst_clk_export => OPEN,
+ bf_unit_reg_st_sst_read_export => bf_unit_reg_st_sst_mosi.rd,
+ bf_unit_reg_st_sst_readdata_export => bf_unit_reg_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ bf_unit_reg_st_sst_reset_export => OPEN,
+ bf_unit_reg_st_sst_write_export => bf_unit_reg_st_sst_mosi.wr,
+ bf_unit_reg_st_sst_writedata_export => bf_unit_reg_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ eth1g_tse_address_export => eth1g_tse_mosi.address(10-1 DOWNTO 0),
+ eth1g_tse_clk_export => OPEN,
+ eth1g_tse_read_export => eth1g_tse_mosi.rd,
+ eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_tse_reset_export => OPEN,
+ eth1g_tse_write_export => eth1g_tse_mosi.wr,
+ eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ eth1g_tse_waitrequest => eth1g_tse_miso.waitrequest,
+
+ eth1g_reg_address_export => eth1g_reg_mosi.address(4-1 DOWNTO 0),
+ eth1g_reg_clk_export => OPEN,
+ eth1g_reg_read_export => eth1g_reg_mosi.rd,
+ eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_reg_reset_export => OPEN,
+ eth1g_reg_write_export => eth1g_reg_mosi.wr,
+ eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ eth1g_ram_address_export => eth1g_ram_mosi.address(10-1 DOWNTO 0),
+ eth1g_ram_clk_export => OPEN,
+ eth1g_ram_read_export => eth1g_ram_mosi.rd,
+ eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_ram_reset_export => OPEN,
+ eth1g_ram_write_export => eth1g_ram_mosi.wr,
+ eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(3-1 DOWNTO 0),
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_epcs_address_export => reg_epcs_mosi.address(3-1 DOWNTO 0),
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_remu_address_export => reg_remu_mosi.address(3-1 DOWNTO 0),
+ reg_remu_clk_export => OPEN,
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_remu_reset_export => OPEN,
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_ppsh_address_export => reg_ppsh_mosi.address(1-1 DOWNTO 0),
+ reg_ppsh_clk_export => OPEN,
+ reg_ppsh_read_export => reg_ppsh_mosi.rd,
+ reg_ppsh_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_ppsh_reset_export => OPEN,
+ reg_ppsh_write_export => reg_ppsh_mosi.wr,
+ reg_ppsh_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_unb_system_info_address_export => reg_unb_system_info_mosi.address(5-1 DOWNTO 0),
+ reg_unb_system_info_clk_export => OPEN,
+ reg_unb_system_info_read_export => reg_unb_system_info_mosi.rd,
+ reg_unb_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_system_info_reset_export => OPEN,
+ reg_unb_system_info_write_export => reg_unb_system_info_mosi.wr,
+ reg_unb_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ rom_unb_system_info_address_export => rom_unb_system_info_mosi.address(10-1 DOWNTO 0),
+ rom_unb_system_info_clk_export => OPEN,
+ rom_unb_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_unb_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ rom_unb_system_info_reset_export => OPEN,
+ rom_unb_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_unb_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_wdi_address_export => reg_wdi_mosi.address(1-1 DOWNTO 0),
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+
+END str;
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys b/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys
index 2ce48c5e9867ca5a417e832152ba86b3f9b43ea1..e304e1cf68c4d3ce0e11d7ccf95364d32700f5c3 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys
@@ -408,6 +408,196 @@
type = "boolean";
}
}
+
+ element eth1g_tse.mem
+ {
+ datum baseAddress
+ {
+ value = 24576;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element eth1g_reg.mem
+ {
+ datum baseAddress
+ {
+ value = 28672;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element eth1g_ram.mem
+ {
+ datum baseAddress
+ {
+ value = 32768;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = 36864;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element reg_epcs.mem
+ {
+ datum baseAddress
+ {
+ value = 36896;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element reg_remu.mem
+ {
+ datum baseAddress
+ {
+ value = 36928;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element reg_ppsh.mem
+ {
+ datum baseAddress
+ {
+ value = 36960;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element reg_unb_system_info.mem
+ {
+ datum baseAddress
+ {
+ value = 36992;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element rom_unb_system_info.mem
+ {
+ datum baseAddress
+ {
+ value = 40960;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+
+ element reg_wdi.mem
+ {
+ datum baseAddress
+ {
+ value = 45056;
+ type = "long";
+ }
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
@@ -830,90 +1020,450 @@
internal="bf_unit_reg_st_sst.readdata"
type="conduit"
dir="end" />
- <module
-
- kind="altera_avalon_onchip_memory2"
- version="11.1"
- enabled="1"
- name="onchip_memory2_0">
- <parameter name="allowInSystemMemoryContentEditor" value="false" />
- <parameter name="autoInitializationFileName">qsys_input_onchip_memory2_0</parameter>
- <parameter name="blockType" value="M144K" />
- <parameter name="dataWidth" value="32" />
- <parameter name="deviceFamily" value="Stratix IV" />
- <parameter name="dualPort" value="false" />
- <parameter name="initMemContent" value="true" />
- <parameter name="initializationFileName" value="onchip_memory2_0" />
- <parameter name="instanceID" value="NONE" />
- <parameter name="memorySize" value="131072" />
- <parameter name="readDuringWriteMode" value="DONT_CARE" />
- <parameter name="simAllowMRAMContentsFile" value="false" />
- <parameter name="simMemInitOnlyFilename" value="0" />
- <parameter name="singleClockOperation" value="false" />
- <parameter name="slave1Latency" value="1" />
- <parameter name="slave2Latency" value="1" />
- <parameter name="useNonDefaultInitFile" value="true" />
- <parameter name="useShallowMemBlocks" value="false" />
- <parameter name="writable" value="true" />
- </module>
- <module
- kind="altera_avalon_jtag_uart"
- version="11.1"
- enabled="1"
- name="jtag_uart_0">
- <parameter name="allowMultipleConnections" value="false" />
- <parameter name="hubInstanceID" value="0" />
- <parameter name="readBufferDepth" value="64" />
- <parameter name="readIRQThreshold" value="8" />
- <parameter name="simInputCharacterStream"><![CDATA[a
-q]]></parameter>
- <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
- <parameter name="useRegistersForReadBuffer" value="false" />
- <parameter name="useRegistersForWriteBuffer" value="false" />
- <parameter name="useRelativePathForSimFile" value="false" />
- <parameter name="writeBufferDepth" value="64" />
- <parameter name="writeIRQThreshold" value="8" />
- </module>
- <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
- <parameter name="bitClearingEdgeCapReg" value="false" />
- <parameter name="bitModifyingOutReg" value="false" />
- <parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="25000000" />
- <parameter name="direction" value="Output" />
- <parameter name="edgeType" value="RISING" />
- <parameter name="generateIRQ" value="false" />
- <parameter name="irqType" value="LEVEL" />
- <parameter name="resetValue" value="0" />
- <parameter name="simDoTestBenchWiring" value="false" />
- <parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="1" />
- </module>
- <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
- <parameter name="alwaysRun" value="true" />
- <parameter name="counterSize" value="32" />
- <parameter name="fixedPeriod" value="true" />
- <parameter name="period" value="1" />
- <parameter name="periodUnits" value="MSEC" />
- <parameter name="resetOutput" value="false" />
- <parameter name="snapshot" value="false" />
- <parameter name="systemFrequency" value="25000000" />
- <parameter name="timeoutPulseOutput" value="false" />
- <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
- </module>
- <module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu_0">
- <parameter name="setting_showUnpublishedSettings" value="false" />
- <parameter name="setting_showInternalSettings" value="false" />
- <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
- <parameter name="setting_preciseIllegalMemAccessException" value="false" />
- <parameter name="setting_preciseDivisionErrorException" value="false" />
- <parameter name="setting_performanceCounter" value="false" />
- <parameter name="setting_illegalMemAccessDetection" value="false" />
- <parameter name="setting_illegalInstructionsTrap" value="false" />
- <parameter name="setting_fullWaveformSignals" value="false" />
- <parameter name="setting_extraExceptionInfo" value="false" />
- <parameter name="setting_exportPCB" value="false" />
- <parameter name="setting_debugSimGen" value="false" />
- <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+
+ <interface
+ name="eth1g_tse_reset"
+ internal="eth1g_tse.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_clk"
+ internal="eth1g_tse.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_address"
+ internal="eth1g_tse.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_write"
+ internal="eth1g_tse.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_writedata"
+ internal="eth1g_tse.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_read"
+ internal="eth1g_tse.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_readdata"
+ internal="eth1g_tse.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="eth1g_reg_reset"
+ internal="eth1g_reg.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_clk"
+ internal="eth1g_reg.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_address"
+ internal="eth1g_reg.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_write"
+ internal="eth1g_reg.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_writedata"
+ internal="eth1g_reg.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_read"
+ internal="eth1g_reg.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_readdata"
+ internal="eth1g_reg.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="eth1g_ram_reset"
+ internal="eth1g_ram.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_clk"
+ internal="eth1g_ram.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_address"
+ internal="eth1g_ram.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_write"
+ internal="eth1g_ram.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_writedata"
+ internal="eth1g_ram.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_read"
+ internal="eth1g_ram.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_readdata"
+ internal="eth1g_ram.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="reg_unb_sens_reset"
+ internal="reg_unb_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_clk"
+ internal="reg_unb_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_address"
+ internal="reg_unb_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_write"
+ internal="reg_unb_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_writedata"
+ internal="reg_unb_sens.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_read"
+ internal="reg_unb_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_readdata"
+ internal="reg_unb_sens.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="reg_epcs_reset"
+ internal="reg_epcs.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_clk"
+ internal="reg_epcs.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_address"
+ internal="reg_epcs.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_write"
+ internal="reg_epcs.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_writedata"
+ internal="reg_epcs.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_read"
+ internal="reg_epcs.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_readdata"
+ internal="reg_epcs.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_clk"
+ internal="reg_remu.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_address"
+ internal="reg_remu.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_write"
+ internal="reg_remu.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_writedata"
+ internal="reg_remu.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_read"
+ internal="reg_remu.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="reg_ppsh_reset"
+ internal="reg_ppsh.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ppsh_clk"
+ internal="reg_ppsh.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ppsh_address"
+ internal="reg_ppsh.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ppsh_write"
+ internal="reg_ppsh.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ppsh_writedata"
+ internal="reg_ppsh.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ppsh_read"
+ internal="reg_ppsh.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ppsh_readdata"
+ internal="reg_ppsh.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="reg_unb_system_info_reset"
+ internal="reg_unb_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_system_info_clk"
+ internal="reg_unb_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_system_info_address"
+ internal="reg_unb_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_system_info_write"
+ internal="reg_unb_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_system_info_writedata"
+ internal="reg_unb_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_system_info_read"
+ internal="reg_unb_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_system_info_readdata"
+ internal="reg_unb_system_info.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="rom_unb_system_info_reset"
+ internal="rom_unb_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_unb_system_info_clk"
+ internal="rom_unb_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_unb_system_info_address"
+ internal="rom_unb_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_unb_system_info_write"
+ internal="rom_unb_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_unb_system_info_writedata"
+ internal="rom_unb_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_unb_system_info_read"
+ internal="rom_unb_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_unb_system_info_readdata"
+ internal="rom_unb_system_info.readdata"
+ type="conduit"
+ dir="end" />
+
+ <interface
+ name="reg_wdi_reset"
+ internal="reg_wdi.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_clk"
+ internal="reg_wdi.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_address"
+ internal="reg_wdi.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_write"
+ internal="reg_wdi.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_writedata"
+ internal="reg_wdi.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_read"
+ internal="reg_wdi.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_readdata"
+ internal="reg_wdi.readdata"
+ type="conduit"
+ dir="end" />
+ <module
+
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">qsys_input_onchip_memory2_0</parameter>
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="true" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="25000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="25000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="setting_bit31BypassDCache" value="true" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="setting_bhtIndexPcOnly" value="false" />
@@ -989,7 +1539,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='pio_wdi.s1' start='0x100' end='0x110' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x110' end='0x118' /><slave name='pio_pps.mem' start='0x118' end='0x120' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='bf_unit_ram_ss_ss_wide.mem' start='20480' end='20482' /><slave name='bf_unit_ram_bf_weights.mem' start='20608' end='20611' /><slave name='bf_unit_ram_st_sst.mem' start='20736' end='20738' /><slave name='bf_unit_reg_st_sst.mem' start='20992' end='20995' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='pio_wdi.s1' start='0x100' end='0x110' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x110' end='0x118' /><slave name='pio_pps.mem' start='0x118' end='0x120' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='bf_unit_ram_ss_ss_wide.mem' start='20480' end='20482' /><slave name='bf_unit_ram_bf_weights.mem' start='20608' end='20611' /><slave name='bf_unit_ram_st_sst.mem' start='20736' end='20738' /><slave name='bf_unit_reg_st_sst.mem' start='20992' end='20995' /><slave name='eth1g_tse.mem' start='24576' end='24580' /><slave name='eth1g_reg.mem' start='28672' end='28674' /><slave name='eth1g_ram.mem' start='32768' end='32772' /><slave name='reg_unb_sens.mem' start='36864' end='36866' /><slave name='reg_epcs.mem' start='36896' end='36898' /><slave name='reg_remu.mem' start='36928' end='36930' /><slave name='reg_ppsh.mem' start='36960' end='36960' /><slave name='reg_unb_system_info.mem' start='36992' end='36995' /><slave name='rom_unb_system_info.mem' start='40960' end='40964' /><slave name='reg_wdi.mem' start='45056' end='45056' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="25000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
@@ -1013,56 +1563,126 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
- <parameter name="g_adr_w" value="5" />
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_input">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_ram_ss_ss_wide">
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_ram_bf_weights">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_ram_st_sst">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_reg_st_sst">
+ <parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
- <parameter name="g_adr_w" value="1" />
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="eth1g_tse">
+ <parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
- <parameter name="g_adr_w" value="1" />
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="eth1g_reg">
+ <parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="eth1g_ram">
<parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="clock_source" version="11.1" enabled="1" name="clk_input">
- <parameter name="clockFrequency" value="25000000" />
- <parameter name="clockFrequencyKnown" value="true" />
- <parameter name="inputClockFrequency" value="0" />
- <parameter name="resetSynchronousEdges" value="NONE" />
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
-
- <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_ram_ss_ss_wide">
- <parameter name="g_adr_w" value="4" />
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_epcs">
+ <parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_ram_bf_weights">
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_remu">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_ppsh">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+
+
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_system_info">
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_ram_st_sst">
- <parameter name="g_adr_w" value="3" />
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_unb_system_info">
+ <parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="bf_unit_reg_st_sst">
- <parameter name="g_adr_w" value="6" />
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
@@ -1450,4 +2070,244 @@ q]]></parameter>
version="11.1"
start="clk_input.clk"
end="bf_unit_reg_st_sst.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="eth1g_tse.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth1g_tse.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="24576" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="eth1g_tse.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="eth1g_tse.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="eth1g_reg.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth1g_reg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="28672" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="eth1g_reg.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="eth1g_reg.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="eth1g_ram.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="eth1g_ram.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="32768" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="eth1g_ram.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="eth1g_ram.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="36864" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_unb_sens.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="36896" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_epcs.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="36928" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_remu.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_ppsh.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_ppsh.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="36960" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_ppsh.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_ppsh.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_unb_system_info.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="36992" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_unb_system_info.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_unb_system_info.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="rom_unb_system_info.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_unb_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="40960" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="rom_unb_system_info.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="rom_unb_system_info.system" />
+
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="45056" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_wdi.system" />
</system>