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Commit e9ec84e0 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added MM master generation.

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tools/oneclick/components/bf_unit.py
+ 5
− 5
View file @ e9ec84e0
......@@ -62,11 +62,11 @@ class bf_unit(Component):
self.vhdl_file_name = None
self.set_vhdl_strings(self, VHDL_INST, VHDL_CONSTANTS, VHDL_SIGNALS, VHDL_LIB)
self.mm_regs = [ ('bf_unit_ram_ss_ss_wide', 4), \
('bf_unit_ram_bf_weights', 5), \
('bf_unit_ram_st_sst' , 3), \
('bf_unit_reg_st_sst' , 6) ] # FIXME These address spans should be derived from parameters
#name, addr_w, RL, force base addr
self.mm_regs = [ ('bf_unit_ram_ss_ss_wide', 4, 1, None), \
('bf_unit_ram_bf_weights', 5, 1, None), \
('bf_unit_ram_st_sst' , 3, 1, None), \
('bf_unit_reg_st_sst' , 6, 1, None) ] # FIXME These address spans should be derived from parameters
# self.set_output('snk_in_arr', (nof_streams, data_width))
# self.set_output('src_out', (data_width))
......
tools/oneclick/components/component.py
+ 7
− 5
View file @ e9ec84e0
......@@ -355,7 +355,7 @@ class Component(mp.Process):
self.terminate_components()
def generate(self, target_vhdl_file=None):
if self.components != []:
if self.components != []: # Sub-components determine the contents of this generated file (e.g. top level)
target_vhdl_file = open(self.vhdl_file_name, "w")
###############################################################################
# ASTRON HEADER, INFO
......@@ -441,7 +441,6 @@ class Component(mp.Process):
###############################################################################
# Iterate through internal components
for component in self.components:
component.generate()
target_vhdl_file.write(component.vhdl_name_comment_block)
......@@ -464,10 +463,10 @@ class Component(mp.Process):
hdllib_file.write('synth_files =\n')
for component in self.components:
if component.vhdl_file_name != None:
hdllib_file.write(' %s\n' %component.vhdl_file_name)
hdllib_file.write(' %s\n' %self.vhdl_file_name)
hdllib_file.write(' ../%s\n' %component.vhdl_file_name)
hdllib_file.write(' ../%s\n' %self.vhdl_file_name)
hdllib_file.write('test_bench_files =\n')
hdllib_file.write(' generated/tb_%s.vhd\n' %self.name)
hdllib_file.write(' tb_%s.vhd\n' %self.name)
hdllib_file.write('quartus_copy_files =\n')
hdllib_file.write(' qsys_mm_master.qsys .\n')
......@@ -496,6 +495,9 @@ class Component(mp.Process):
pin_file.write('source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl\n')
pin_file.close()
for component in self.components: # Chance for subcomponents to run their own overloaded generate()
component.generate()
def get_vhdl_instance(self):
# Only base components have a pre-declared VHDL instance. Composites do not.
if hasattr(self, 'vhdl_instance'):
......
tools/oneclick/components/ctrl_unb1_board.py
+ 11
− 1
View file @ e9ec84e0
......@@ -170,7 +170,17 @@ class ctrl_unb1_board(Component):
self.set_vhdl_strings(self, VHDL_INST, VHDL_CONSTANTS, VHDL_SIGNALS, VHDL_LIB)
self.vhdl_port_declarations = VHDL_PORT_DECLARATIONS
#name, addr_w, RL, force base addr
self.mm_regs = [ ('eth1g_tse', 10, 0, None), \
('eth1g_reg', 4, 1, None), \
('eth1g_ram', 10, 1, None), \
('reg_unb_sens', 3, 1, None), \
('reg_epcs', 3, 1, None), \
('reg_remu', 3, 1, None), \
('reg_ppsh', 1, 1, None), \
('reg_unb_system_info', 5, 1, 0x0), \
('rom_unb_system_info', 10, 1, 0x1000), \
('reg_wdi', 1, 1, None)]
# self.set_output('snk_in_arr', (nof_streams, data_width)) # UDP offload
# self.set_output('src_out_arr', (data_width)) # UDP offload
......
tools/oneclick/components/mm_master.py
+ 170
− 11
View file @ e9ec84e0
......@@ -9,14 +9,83 @@ VHDL_INST_TOP = """ u_mm_master : ENTITY work.mm_master
PORT MAP(
mm_rst => mm_rst,
mm_clk => mm_clk,
"""
eth1g_mm_rst => eth1g_mm_rst,
eth1g_reg_interrupt => eth1g_reg_interrupt,
pout_wdi => pout_wdi"""
VHDL_INST_BOTTOM = """
-- PIOs
pout_wdi => pout_wdi
);
"""
VHDL_ENTITY_TOP = """
ENTITY DESIGN_NAME IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
eth1g_reg_interrupt : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC"""
VHDL_ENTITY_BOTTOM = """
);
END DESIGN_NAME;
"""
# FIXME - The coe_* should all be renamed to new style as it makes automation impossible.
QSYS_INST_BEGIN = """
mm_rst_n <= NOT mm_rst;
gen_qsys_mm_master : IF g_sim = FALSE GENERATE
u_qsys_mm_master : qsys_mm_master
PORT MAP (
clk_0 => mm_clk,
reset_n => mm_rst_n,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_irq => eth1g_reg_interrupt,
out_port_from_the_pio_wdi => pout_wdi"""
QSYS_EXPORT_PORT_MAP = """ $name_address_export => $name_mosi.address($addr_width-1 DOWNTO 0),
$name_clk_export => OPEN,
$name_read_export => $name_mosi.rd,
$name_readdata_export => $name_miso.rddata(c_word_w-1 DOWNTO 0),
$name_reset_export => OPEN,
$name_write_export => $name_mosi.wr,
$name_writedata_export => $name_mosi.wrdata(c_word_w-1 DOWNTO 0)"""
QSYS_INST_END = """
);
END GENERATE;
"""
QSYS_COMPONENT_DECLARATION_BEGIN = """
COMPONENT QSYS_MM_MASTER IS
PORT (
clk_0 : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
eth1g_irq : IN STD_LOGIC;
out_port_from_the_pio_wdi : OUT STD_LOGIC"""
QSYS_COMPONENT_DECLARATION_PORT_MAP = """ $name_address_export : OUT STD_LOGIC_VECTOR($addr_width-1 DOWNTO 0);
$name_clk_export : OUT STD_LOGIC;
$name_read_export : OUT STD_LOGIC;
$name_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
$name_reset_export : OUT STD_LOGIC;
$name_write_export : OUT STD_LOGIC;
$name_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)"""
QSYS_COMPONENT_DECLARATION_END = """
);
END COMPONENT QSYS_MM_MASTER;
"""
class mm_master(Component):
"""
......@@ -27,6 +96,8 @@ class mm_master(Component):
def __init__(self, slave_components):
Component.__init__(self, name='mm_master')
self.slave_components = slave_components
# Create a list of peripherals to pass to QSYS generator
peripheral_list = []
base_address = 0x5000
......@@ -54,16 +125,104 @@ class mm_master(Component):
# Create MMM wrapper for the generated QSYS
# . No Python function to call, so we need to execute the mmm_gen.py script on the command line?
# FIXME - mmm_gen.py errors out.
# FIXME - mmm_gen.py errors out and is difficult to integrate. Using self.generate() isntead.
# # Create the correct port mapping
# self.vhdl_inst_mid = ''
# for slave_component in slave_components:
# print slave_component.vhdl_signals
# self.vhdl_instance = VHDL_INST_TOP+self.vhdl_inst_mid+VHDL_INST_BOTTOM
# Create this (mm_master.vhd) VHDL instance
vhdl_inst_mid = ''
for slave_component in slave_components:
for mm_reg in slave_component.mm_regs:
# print mm_reg
name = mm_reg[0]
vhdl_inst_mid+=',\n %s_mosi => %s_mosi,\n %s_miso => %s_miso' %(name,name,name,name)
# print vhdl_inst_mid
self.vhdl_instance = VHDL_INST_TOP+vhdl_inst_mid+VHDL_INST_BOTTOM
self.vhdl_lib = ''
def generate(self):
target_vhdl_file = open(self.vhdl_file_name, "w")
###############################################################################
# ASTRON HEADER, INFO
###############################################################################
target_vhdl_file.write(ASTRON_HEADER)
target_vhdl_file.write('\n')
###############################################################################
# USED LIBRARIES
###############################################################################
target_vhdl_file.write(STANDARD_LIBS)
###############################################################################
# ENTITY DECLARATION
###############################################################################
target_vhdl_file.write(VHDL_ENTITY_TOP.replace('DESIGN_NAME', self.name))
vhdl_entity_mid = ''
for slave_component in self.slave_components:
for mm_reg in slave_component.mm_regs:
# print mm_reg
name = mm_reg[0]
vhdl_entity_mid+=';\n %s_mosi : OUT t_mem_mosi;\n %s_miso : IN t_mem_miso' %(name,name)
target_vhdl_file.write(vhdl_entity_mid)
target_vhdl_file.write(VHDL_ENTITY_BOTTOM.replace('DESIGN_NAME', self.name))
###############################################################################
# ARCHITECTURE DECLARATION
###############################################################################
target_vhdl_file.write('ARCHITECTURE str OF %s IS\n\n' %self.name)
###############################################################################
# CONSTANT, SIGNAL, COMPONENT DECLARATIONS
###############################################################################
target_vhdl_file.write(QSYS_COMPONENT_DECLARATION_BEGIN)
qsys_comp_decl = ''
for slave_component in self.slave_components:
for mm_reg in slave_component.mm_regs:
# print mm_reg
name = mm_reg[0]
addr_width = mm_reg[1]
rl=mm_reg[2]
qsys_comp_decl+=';\n\n'+QSYS_COMPONENT_DECLARATION_PORT_MAP.replace('$name', name).replace('$addr_width', str(addr_width))
if rl==0:
qsys_comp_decl+=';\n\n %s_waitrequest : IN STD_LOGIC' %(name)
target_vhdl_file.write(qsys_comp_decl)
target_vhdl_file.write(QSYS_COMPONENT_DECLARATION_END)
target_vhdl_file.write(' SIGNAL mm_rst_n : STD_LOGIC;\n')
###############################################################################
# ARCHITECTURE BEGIN
###############################################################################
target_vhdl_file.write('BEGIN\n')
###############################################################################
# QSYS INSTANCE
###############################################################################
target_vhdl_file.write(QSYS_INST_BEGIN)
qsys_inst_mid = ''
for slave_component in self.slave_components:
for mm_reg in slave_component.mm_regs:
# print mm_reg
name = mm_reg[0]
addr_width = mm_reg[1]
rl=mm_reg[2]
qsys_inst_mid+=',\n\n'+QSYS_EXPORT_PORT_MAP.replace('$name', name).replace('$addr_width', str(addr_width))
if rl==0:
qsys_inst_mid+=',\n\n %s_waitrequest => %s_miso.waitrequest' %(name,name)
target_vhdl_file.write(qsys_inst_mid)
target_vhdl_file.write(QSYS_INST_END)
###############################################################################
# ARCHITECTURE END
###############################################################################
target_vhdl_file.write('\nEND str;\n')
target_vhdl_file.close()
def run(self):
# No model
pass
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