Use hdl_lib_include_ip instead of hdl_lib_excludes.

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -3,9 +3,7 @@ hdl_library_clause_name = unb1_ddr3_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth diagnostics io_ddr tech_ddr
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
@@ -16,7 +14,6 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_unb1_ddr3.vhd
 
-
 [modelsim_project_file]
 modelsim_compile_ip_files =
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg

@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_ddr3_reorder_dual_rank_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave 
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave 
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master                   
-                   ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =   
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg

@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_ddr3_reorder_single_rank_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master 
-                   ip_stratixiv_ddr3_uphy_4g_800_slave 
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave 
-                   ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =   
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd

boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = unb1_ddr3_transpose_lib
 hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd