From 455a4103bf2d99b91a61964da149e010da554e27 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 28 Apr 2016 13:13:15 +0000
Subject: [PATCH] Use hdl_lib_include_ip instead of hdl_lib_excludes.
---
boards/uniboard1/designs/unb1_ddr3/hdllib.cfg | 5 +----
.../revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg | 5 +----
.../revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg | 5 +----
boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg | 2 +-
4 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 5c7bc018d7..b24fe5c0be 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -3,9 +3,7 @@ hdl_library_clause_name = unb1_ddr3_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth diagnostics io_ddr tech_ddr
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
- ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
- ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
@@ -16,7 +14,6 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_ddr3.vhd
-
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index a788059ab4..8be0a5b4fb 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_ddr3_reorder_dual_rank_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
- ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
- ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
- ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index ab76e6abc4..104d038b62 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_ddr3_reorder_single_rank_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
- ip_stratixiv_ddr3_uphy_4g_800_slave
- ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
- ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 3d32971246..97059fae53 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = unb1_ddr3_transpose_lib
hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
--
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