diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 5c7bc018d7b9c72a00c35cf3425bd4f271b248fe..b24fe5c0be88b413b816bef23046129c18351227 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -3,9 +3,7 @@ hdl_library_clause_name = unb1_ddr3_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth diagnostics io_ddr tech_ddr
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
@@ -16,7 +14,6 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_unb1_ddr3.vhd
 
-
 [modelsim_project_file]
 modelsim_compile_ip_files =
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index a788059ab4272716edf1f8bce56dfdb2c3fbe114..8be0a5b4fb90c86b342091e5454803b6feb16053 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_ddr3_reorder_dual_rank_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave 
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave 
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master                   
-                   ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =   
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index ab76e6abc4b0772bae353b2895e5927e873f5622..104d038b62b71f7be03522443c9e637290e17ba3 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb1_ddr3_reorder_single_rank_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master 
-                   ip_stratixiv_ddr3_uphy_4g_800_slave 
-                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave 
-                   ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =   
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 3d329712469c43eeaf81adb6a9f96397a6e26e22..97059fae5345f036cb41815eab7139b7b0a3809a 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = unb1_ddr3_transpose_lib
 hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd