Excluding new DDR3 single rank ip version

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -4,6 +4,8 @@ hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth diagnostics io_d
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
 
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd