From 44dd2c25001cda6e250c49c4db9cf41350a0a524 Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Fri, 8 May 2015 11:23:46 +0000
Subject: [PATCH] Excluding new DDR3 single rank ip version

---
 boards/uniboard1/designs/unb1_ddr3/hdllib.cfg | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 5a0b7fed47..32ac853ff1 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -4,6 +4,8 @@ hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth diagnostics io_d
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+                   ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
 
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
-- 
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