Merge branch 'master' of git.astron.nl:desp/hdl

applications/lofar2/doc/prestudy/station2_sdp_dsp.txt

@@ -44,10 +44,20 @@ M&C:
     
     The (x+y) could be implemented as first (x+y) and then *w, or as first weight and then add. 
 
+
 *******************************************************************************
 * Subband correlator
 *******************************************************************************
 
+- Subband select of N_crosslets local crosslets per signal input
+- Interleave local crosslets from S_pn = 12 signal inputs
+- XC ring
+- XC dispatcher of local and remote crosslets
+- X_sq correlator cell with N_crosslets * S_pn*S_pn visibilities and N_valid, N_flagged counts
+- M&C:
+  . Subband select
+  . XC ring 
+  . X_sq 
 
 
 

applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt

@@ -23,7 +23,7 @@ Definitions
 Introduction
 - Context
   . ADD fig 3.1-1 (E)ICD and L3 PBS overview
-- Scope
+- Scope and purpose
 - Document overview
 
 Station overview

applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt

@@ -3,24 +3,24 @@
 *******************************************************************************
 Includes design, implementation, verification on HW, technical commissioning.
 
-v1  v2 
+v1  v2
        Infrastructure
 10  20   - Development environment using GIT, RadioHDL, updating existing components
 20   .   - BSP using Gemini Protocol, ARGS
 10   .   - Ethernet access (OSI 1-4)
 10  20   - Ring access
-     
-       Applications:
+
+       Application:
 15   .   - ADC ingress and time stamp
 20  10   - Subband filterbank (critically sampled)
  0  30   - Subband filterbank (oversampled)
 10   .   - Beamformer
 20   .   - Subband correlator
-25   .   - Transient buffer (DDR4 interface, subband select and DM >= 0, packet format, M&C, RW access via M&C) 
+25   .   - Transient buffer (DDR4 interface, subband select and DM >= 0, packet format, M&C, RW access via M&C)
 20   .   - Transient detection
 20   .   - Subband offload
  0   .   - 160 MHz
-     
+
 35   . Integration
      5   - FPGA pinning
     10   - Interface test designs unb2c
@@ -41,7 +41,7 @@ v2 : 10 less for critically sampled PFB
 
 ==> EK, JH: v1 estimate of April 2019 is still valid as v2 on 10 Oct 2019.
 
-v3 : 
+v3 :
 
    Infrastructure
 20   - Development environment using GIT, RadioHDL, updating existing components
@@ -51,7 +51,7 @@ v3 :
 20   - Ring access
 10   - 10GbE access (OSI 1-4)
 
-   Applications:
+   Application:
 15   - ADC input and time stamp
 10   - Subband filterbank (critically sampled)
 20   - Subband correlator
@@ -61,7 +61,7 @@ v3 :
 20   - Transient detection
 30   - Oversampled subband filterbank
  0   - Support 160 MHz
- 
+
    Integration:
 10   - Lab tests
  5   - Technical commissioning Dwingeloo
@@ -73,3 +73,147 @@ All:
 No oversampled filterbank:
 20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 +       0 + 10 + 5 + 5 = 225
 
+
+
+
+*******************************************************************************
+* SDP Workpackage (UniBoard2 HW + FW)
+*******************************************************************************
+
+Firmware FPGA images:
+- the SDP has one main firmware design unb2c_sdp,
+- the integrated design of SDP is revision unb2c_sdp_station,
+- per task there are revisions of unb2c_sdp that contain subsets of the SDP functionality,
+ 
+
+Deliverables (D): items that are needed for a milestone
+Milestones (M) : 'cake moments' when you demonstrate deliverables
+- integration passed
+- review passed
+
+
+Tasks:
+
+INFRASTRUCTURE UniBoard2:
+  weeks  nr task
+     20  1) Maintain firmware development environment
+            - using GIT
+            - using RadioHDL
+            - updating existing VHDL library components
+            D=> Operational firmware development environment
+            D=> VHDL libraries verified in simulation
+
+         2) UniBoard2 board and test firmware
+            - unb2c board HW
+            D=> unb2c board detailed design document
+            D=> unb2c board schematic
+            D=> unb2c board layout
+            
+            M=> unb2c board detailed design document review (unb2b modifications)
+            M=> unb2c board schematic review
+            M=> unb2c board layout review (production ready)
+            M=> unb2c board lab validation using JTAG, unb2c_test designs OK
+            M=> unb2c board production validation using JTAG, unb2c_minimal_gmi OK
+            
+      5     - unb2c FPGA pinning design
+     10     - unb2c FPGA interface test designs
+            D=> unb2c_test design revisions (1GbE, 10GbE, DDR4, flash, ADC)
+            D=> unb2c_test_adc (read ADC samples from multiple inputs)
+            
+
+     20  3) UniBoard2 board support package (BSP)
+            - M&C by SCU via Gemini protocol
+            - M&C interface definition and generation using ARGS (doc, C, HDL)
+            D=> Gemini board for SCU M&C tests
+            D=> unb2c_minimal_gmi (1GbE, flash)
+            M=> unb2c_minimal_gmi validated using M&C by SCU (read design name)
+
+INFRASTRUCTURE SDP:
+     10  4) Network access via 10GbE
+            - Ethernet MAC, UDP/IPv4, ARP, ping
+            D=> 10GbE HDL component including support for UDP/IPv4, ARP, ping
+            D=> unb2c_10GbE
+            M=> unb2c_10GbE validated using data capture on PC and ping
+
+     20  5) Ring access using test data and BSN monitor
+            D=> unb2c_ring_combiner for BF
+            D=> unb2c_ring_multicast for XC
+            D=> unb2c_ring_endcast for SO, TB
+            M=> unb2c_ring revisions verified in simulation
+            M=> unb2c_ring revisions validated on hardware using M&C on SCU
+
+APPLICATION SDP documents:
+         6) Required documents
+            D=> Detailed design document of SDP firmware
+            D=> L1 ICD-11109 SDP-CEP: beamlet data protocol
+            D=> L1 ICD-11109 SDP-CEP: transient data protocol
+            D=> L2 ICD-11211 SC-SDP: FW register map and register definitions
+            D=> L2 ICD-11211 SC-SDP: UniBoard2 hardware M&C
+            D=> L2 ICD-11207 RCU2S-SDP: ADC interface
+            D=> L2 ICD-11209 STF-SDP: Time and frequency interface
+            D=> L2 ICD-11218 SDP-STCA: Subrack interface
+            
+            M=> SDP detailed design and interface documents ready for DDR
+            M=> SDP detailed design and interface documents updated for CDR
+            
+            D=> SDP firmware verification and maintenance document
+            M=> SDP all documents finished
+
+APPLICATION single node:
+  weeks  nr task
+     15  7) ADC input and timestamp (RCU2 interface)
+            ==> unb2c_sdp_adc_capture, read ADC or WG samples from databuffer via M&C
+            ==> unb2c_sdp_station (ADC)
+            
+
+M=> SDP ready for CDR
+    All major technical UniBoard2 hardware and SDP firmware risks are mitigated (by design and
+    based on validation with at least two UniBoard2 using JTAG, unb2c_minimal_gmi, unb2c_ring,
+    and unb2c_sdp_adc_capture).
+
+
+     10  8) Subband filterbank (Fsub)
+            ==> unb2c_sdp_filterbank to read SST via M&C
+            ==> unb2c_sdp_station (ADC + SST)
+
+APPLICATION multi node:
+  weeks  nr task
+     20  9) Subband correlator (XC)
+            ==> unb2c_sdp_correlator_one_node, read XST via M&C and create ACM for one node
+            ==> unb2c_sdp_correlator_multi_node, read XST via M&C and use ring to create complete ACM
+            ==> unb2c_sdp_station (ADC + SST + XST)
+
+APPLICATION multi node / network output:
+  weeks  nr task
+     10 10) Beamformer (BF)
+            ==> unb2c_sdp_beamformer_bst_one_node, read BST via M&C
+            ==> unb2c_sdp_beamformer_output_one_input, output to CEP for one input from one node
+            ==> unb2c_sdp_beamformer_output_one_node, output to CEP and sum one node
+            ==> unb2c_sdp_beamformer_output_multi_node, output to CEP and use ring to sum nodes
+            ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output)
+            ==> detailed design doc
+            
+     25 11) Transient buffer (TB)
+            ==> unb2c_sdp_transient_buffer revisions (ADC + SST + TB readout, M&C access DDR4)
+            ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout)
+            ==> detailed design doc
+
+     20 12) Transient detection (TD)
+            ==> unb2c_sdp_transient_buffer revisions (ADC + TD event)
+            ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event)
+            ==> detailed design doc
+
+     20 13) Subband offload (SO) for AARTFAAC2.0
+            ==> unb2c_sdp_subband_offload revisions (ADC + SST + SO, one node, all nodes via ring)
+            ==> unb2c_sdp_station (ADC + SST + XST + BST + BF output + TB readout + TD event + SO)
+            ==> detailed design doc
+
+INTEGRATION:
+  weeks  nr task
+     20 14) Station integration tests (using unb2c_sdp_station)
+            - Laboratory tests
+            - Technical commissioning Dwingeloo Test Station ("Huisje West")
+            - Technical commissioning Prototype Test Station
+            - Technical commissioning Pre-production Test Station
+
+

applications/lofar2/doc/prestudy/station2_sdp_timing.txt

@@ -2,42 +2,43 @@
 * Fixed Station BSN grid and the PPS grid
 *******************************************************************************
 
-The Station needs an external trigger to align all ADCs in the RCU2S and all FPGA procesing nodes in the SDP.
-For this trigger a pulse from the pulse per second (PPS) is used. The PPS is aliged to the top of second of the
-UTC time of day (ToD). The PPS is a hardware trigger that is available within the entire SDP at sample clock
-cycle accuracy. Thanks to the Timing Distributor (TD) the PPS trigger is also available as hardware trigger in
-all Stations. Thanks to the TD the PPS is aligned to UTC ToD, and the ToD is available to the Telescope Manager
-(TM) in LOFAR2.0 and to Station Control in each Station. The TM controls, via Station Control, which PPS pulse
-is used to start SDP. The PPS is identified by a Seconds Sequence Number (SSN) that counts PPS since a certain
+The Station needs an external trigger to align all ADCs in the RCU2S and all FPGA procesing nodes
+in the SDP. For this trigger a pulse from the pulse per second (PPS) is used. The PPS is aliged to
+the top of second of the UTC time of day (ToD). The PPS is a hardware trigger that is available
+within the entire SDP at sample clock cycle accuracy. Thanks to the Timing Distributor (TD) the
+PPS trigger is also available as hardware trigger in all Stations. Thanks to the TD the PPS is
+aligned to UTC ToD, and the ToD is available to the Telescope Manager (TM) in LOFAR2.0 and to
+Station Control in each Station. The TM controls, via Station Control, which PPS pulse is used to
+start SDP. The PPS is identified by a Seconds Sequence Number (SSN) that counts PPS since a certain
 date in the past, e.g. t_epoch = 1 jan 1970, but some other fixed date is possible too.
 
-The SDP processes the data in blocks of ADC samples that are identified by a Station block sequence number
-(BSN). The Station BSN time grid should be fixed, so independent of when the data processing starts. Therefore
-the Station BSN counts blocks since the same t_epoch as the SSN, so the t_epoch defines the common reference
-moment in history for the Station BSN grid and for the PPS grid. The PPS grid does not necessarily always
-coincide with the Station BSN grid. The BSN period determines whether the Station BSN can start exactly at an
-PPS or not.
+The SDP processes the data in blocks of ADC samples that are identified by a Station block sequence
+number (BSN). The Station BSN time grid should be fixed, so independent of when the data processing
+starts. Therefore the Station BSN counts blocks since the same t_epoch as the SSN, so the t_epoch
+defines the common reference moment in history for the Station BSN grid and for the PPS grid. The
+PPS grid does not necessarily always coincide with the Station BSN grid. The BSN period determines
+whether the Station BSN can start exactly at an PPS or not.
 
 The processing of the ADC inputs in SDP is done by multiple FPGAs in parallel. Each FPGA has a BSN source that
 creates the Station BSN grid. The BSN source is the wall clock of the FPGA. To be able to start the data
 processing at any PPS it is necessary that the BSN source can start at a programmable fraction of a BSN period
 after the PPS. In this way processing of one Station ADC signal input can be restarted at any PPS (with zero
-phase offset to the other signal input) and an entire Station can be restarted at any PPS (with zero phase 
+phase offset to the other signal input) and an entire Station can be restarted at any PPS (with zero phase
 offset to the other Stations). The BSN source ensures that the BSN timing is always on the fixed Station
 BSN time grid. The initial BSN and the offset fraction of a BSN period need to be provided to SDP via the
 M&C interface by Station Control. Both Station Control and SDP know the PPS grid. Station Control also knows
 UTC and with that information Station Control can program and initialize the BSN source in the FPGAs to start
-counting data blocks at the next PPS. 
+counting data blocks at the next PPS.
 
 The sample frequency f_adc = 200 MHz is an integer number of Hz and locked to the PPS, therefore the PPS grid
 always coincides with the ADC sample period T_adc = 1/f_adc = 5 ns grid. The Station BSN block period is an
 integer number of N_blk sample periods T_adc. The Station BSN period is set by the subband rate of the subband
-polyphase filterbank (PFB), so the Station BSN period is equal to the subband period is T_sub. 
-The input to the subband filterbank is the real signal from the ADC. For both the critically sampled PFB and 
+polyphase filterbank (PFB), so the Station BSN period is equal to the subband period is T_sub.
+The input to the subband filterbank is the real signal from the ADC. For both the critically sampled PFB and
 the oversampled PFB the data block size of the input data is N_blk = N_FFT = 1024 ADC samples, however for the
 oversampled PFB the blocks overlap by a factor R_os. Hence for the critically sampled PFB the BSN period is
 T_sub = N_blk = 1024 [T_adc] and for the oversampled PFB the BSN period is T_sub = N_blk / R_os = 864
-[T_adc], in case R_os = 32/27. At the output of the subband filterbank a data block contains 
+[T_adc], in case R_os = 32/27. At the output of the subband filterbank a data block contains
 N_sub = N_FFT / N_complex = 512 complex subband samples that all correspond to the same time instant as
 defined by the Station BSN. Each subband sample represents another frequency.
 
@@ -50,17 +51,17 @@ of 0:N_blk-1 sample periods. The BSN source starts at a PPS with an initial Stat
 and a BSN offset fraction of:
 
   BSN offset fraction = mod(SSN * 1 s, T_sub) / T_adc = mod(SSN * f_adc, N_blk)
-  
+
 to make sure that the BSN grid is always relative to t_epoch, independent of at which PPS the BSN source was
 started. The Station BSN increments after every block. The time ToD_BSN at the BSN grid is:
 
   ToD_BSN = t_epoch + Station BSN * T_sub
-  
+
 
 Note:
 - The BSN offset fraction could also be compensated for by delaying the sample data in the ADC signal input
   buffers at the input of SDP. Delaying the data does compensate for phase differences in the subband
-  data, but does not compensate for the offset in the BSN grid. The BSN alignment buffers between signal 
+  data, but does not compensate for the offset in the BSN grid. The BSN alignment buffers between signal
   inputs from different FPGAs then still need to compensate for this BSN offset fraction. Hence delaying the
   data is an indirect and incomplete solution, and therefore it is not used.
 - In LOFAR1 the Station BSN is divided in a 32 bit seconds sequence number (SSN) that counts PPS intervals and
@@ -80,7 +81,7 @@ and any M&C upon the data, because:
 
 - It is not necessary to facilitate using an offset 0 < T_sub_o < T_sub to start the BSN grid at an integer
   number of T_adc after t_epoch, because the BSN grid is sufficiently fine.
-- It is not necessary to represent fine group delays of digital filters or analogue electronics and 
+- It is not necessary to represent fine group delays of digital filters or analogue electronics and
   cables in the BSN, because these delays are all accounted for after calibration.
   . Course group delays and cable delay differences can be compensated for in steps to T_adc via the signal
     input buffer of every ADC input in SDP.
@@ -106,7 +107,7 @@ In LOFAR2 the timestamp should be independent of:
 
 - using 200 MHz sample rate or 160 MHz sample rate,
 - using critically sampled subband filterbank or oversampled subband filterbank
-  
+
 If T_sub was fixed then T_sub could be used as timestamp resolution (like in APERTIF). However T_sub depends
 on the type of subband filterbank with a resolution of T_adc. If T_adc was fixed then T_adc could be used
 as timestamp resolution. However T_adc depends on the sample clock rate. Therefore the timestamp resolution
@@ -118,11 +119,11 @@ of 0.2 ns such that they are:
 
  * integer values, and
  * independent of the sample period.
- 
+
 The actual timestamp in fractional seconds of 0.2 ns follows from:
 
   timestamp = Station BSN * T_sub_i * 0.2 [ns].
-  
+
 The BSN and T_sub_i can be specified as:
 
 - single 64 bit integer timestamp value of BSN * T_sub_i [0.2 ns]
@@ -131,7 +132,7 @@ The BSN and T_sub_i can be specified as:
 To cover 116 years for a BSN with smallest T_sub = 4000 ns for R_os = 32/25 = 1.28 requires:
 
   log2( 116 * (365.25 * 24 * 3600 / 4000e-9) ) = 49.7, so 50 bits
-  
+
 Therefore allocate 64b in a packet header to send the BSN information. The BSN and timestamp are direcly
 related via T_sub_i, but the advantage of providing the BSN separately is that it increments by 1 for
 each block period T_sub, so it can be used as block index.
@@ -155,12 +156,12 @@ of the data in a Station. However counting blocks is not sufficient to maintain
 The assumptions are:
 
 - data is transported and processed in blocks,
-- partial blocks cannot occur. 
+- partial blocks cannot occur.
 - the data flow can only stop or continue at block boundaries.
 
 To recover from gaps in the data flow the BSN can be transported along with every data block.
 For the external FPGA interfaces one or more data blocks get packed into the payload and the BSN is then
-transported via the header. The BSN in the header corresponds to the first data block in the payload, the 
+transported via the header. The BSN in the header corresponds to the first data block in the payload, the
 position of a data block in the payload defines the offset to this BSN.
 
 For data transport within the FPGA it is costly from a resource point of view to tranport the 64 bit BSN
@@ -191,10 +192,10 @@ For the blocks between sync pulses the Station BSN is incremented with every blo
 BSN needs to be preserved during the sync interval, then lost or discarded blocks must be replaced by filler
 blocks. Whether only the BSN at the data sync is relevant, or whether also the BSN of subsequent data blocks is
 needed depends on the function. For the statistics (AST, SST, BST, XST) the BSN at the data sync is sufficient to
-mark the timing of integration results. For these integration results the number of data blocks within the 
+mark the timing of integration results. For these integration results the number of data blocks within the
 integration interval is relevant to know how many blocks contributed (and thus also how many blocks were lost).
 However for the integration result it is not relevant which blocks got lost, because the statistics do not have
-to keep accurated time centroid information. It is sufficient to use the BSN at data sync to timestamp the 
+to keep accurated time centroid information. It is sufficient to use the BSN at data sync to timestamp the
 integration results, as if all blocks contributed. As another example, for the beamformer it is important to
 be able to recreate the BSN at the data sync and all subsequent data blocks, because the beamformer must weight
 and sum the input beamlets that coincide in time. Similar for the beamformer output to CEP and for the subband
@@ -253,7 +254,7 @@ because it means that Stations should start at an even sync interval when the PP
 to ensure that all stations remain aligned. Starting only at even PPS ensures that LOFAR1 uses a BSN grid
 that is fixed to t_epoch = 1970. For an oversampled subband filterbank the PPS grid and BSN grid
 coincide every q-th PPS, where R_os = p/q, so then a Station should only start every q-th PPS.
-In APERTIF the sync interval was chosen to be an integer number of fine channel periods T_chan = 
+In APERTIF the sync interval was chosen to be an integer number of fine channel periods T_chan =
 N_Chan * T_sub, which resulted in 12500 T_chan and 800000 T_sub or a period of 1.024 s. This 1.024 s is used
 as unit integration period of the correlator in APERTIF. A sync interval of 1 s would have resulted in
 781250 T_sub and 12207.03125 T_chan. The APERTIF sync interval of 1.024 s is akward too, because it differs
@@ -262,7 +263,7 @@ grid coincide, which is once every 125 s, because 128/125 = 1.024.
 LOFAR1 and APERTIF show that in general application periods do not integer fit with the 1 s PPS grid. For
 integration periods the only two options are to either use another integration interval (like 1.024 s in
 APERTIF) or to accept that the number of samples per integration interval can differs by one (like 195313 or
-195312 in LOFAR1). 
+195312 in LOFAR1).
 Both LOFAR1 and APERTIF cannot start at any PPS without affecting the BSN grid. This needs to be solved for
 LOFAR2.0. Like in LOFAR1, for LOFAR2.0 the PPS grid and BSN grid are fixed to t_epoch = 1970. However,
 instead of waiting until the BSN grid and PPS grid coincide, the BSN source in
@@ -339,14 +340,14 @@ In Station SDP the BSN serves two purposes;
 - the entire BSN provides wall clock time on the BSN grid and is thus linked to UTC,
 - the difference in BSN is used to time align input streams
 
-In Station SDP each FPGA has a local BSN source and a local stream that carries the data from its local ADC 
+In Station SDP each FPGA has a local BSN source and a local stream that carries the data from its local ADC
 signal inputs. The BSN aligner needs to align the local stream with the remote streams that are received
 from the other FPGA via the ring. The maximum BSN latency on the ring depends on the number of FPGAs in the
 ring. Suppose each FPGA introduces a latency of at least one packet, because it applies store and forward on
 packets, and less than two packets. Furthermroe assume that on the ring each packet contains one data block.
 The maximum number of hops between the first FPGA on the ring and the final FPGA is N_FPGA-1. For the LBA
 ring N_FPGA = 16. Hence the maximum BSN latency that can occur within
-SDP is < (N_FPGA-1) * 2 < 32 block periods. Hence the maximum BSN difference between the local input and a 
+SDP is < (N_FPGA-1) * 2 < 32 block periods. Hence the maximum BSN difference between the local input and a
 remote input of the BSN aligner is < 32. Therefore to align the input streams the BSN aligner only has to
 compare the log2(32) = 5 LSbits of the BSN of all input streams. This implies that for the BSN aligner it
 would be sufficient to only transport these bits in the packet header, however it is convenient and not too
@@ -371,6 +372,28 @@ Note:
 
 
 
+Key ideas:
+- Use Ethernet CRC and DP CRC to ensure detection of packet errors and to ensure error free blocks
+  within FPGA firmware
+- Within SDP firmware the BSN at sync can be obtained from the local BSN source and subsequent
+  BSN can be derived by counting blocks:
+  . Use filler blocks to replace lost packets, to maintain BSN count within FPGA firmware
+  . Use local BSN source in FPGA and pass on sync within SDP firmware to know the BSN in the firmware.
+
+
+  RCU2                          Subband        Ring
+                                PFB
+
+                        data            data
+  data ------> BSN    --------> Move, -------> Packet
+  PPSH ------> source   sync    DSP     sync   encoding
+                        BSN .........>  BSN    ring
+
+  Ring                                                            BF, XC
+             data                                         data            data
+  Packet   --------> Validate  --> Validate --> BSN     --------> Move, --------> Packet
+  decoding   sync    CRC           BSN          aligner   sync    DSP     sync    encoding
+  ring       BSN .......................................................> BSN     output
 
 
 
@@ -386,9 +409,7 @@ Design decisions:
   but in simulation it can be much less.
 - Use central UTC timestamp at PPS initialized by M&C and incremented by SDP firmware for the SSN
   per FPGA.
-- Use 32 bit SSN to fit UTC in seconds for 136 years since 1970
-- Use local BSN that counts data blocks within a sync interval, so it restarts at 0 at the internal sync
-- Within SDP transport the sync and the local BSN. The sync is transported via the MSbit of the local BSN.
-  At the sync transport the 31 bit SSN instead of local BSN 0, but only for monitoring purposes.
-- Derive 64 bit UTC timestamp in units of T_sub in SDP firmware and use this for data output to CEP
+- Use 64 bit continuous BSN that counts subband periods since 1970
+- Within SDP transport the sync and the BSN. The sync is transported via the MSbit of the BSN.
+
 

applications/lofar2/doc/prestudy/station2_to_do_erko.txt

@@ -182,15 +182,16 @@ git remote remove <remote name> # remove a remote repo
 *******************************************************************************
 Open issues:
 - Central HDL_IO_FILE_SIM_DIR = build/sim --> Project local sim dir
-- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR copies the
-  last <buildset>, using more than one buildset at a time gices conflicts.
+- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR
+  copies the last <buildset>, using more than one buildset at a time gices conflicts.
 
 
 
 *******************************************************************************
 * To do:
 *******************************************************************************
-- Check that the Expert users (MB, SJW, MN), Maintainers (HM) and Local users are happy with the design decisions
+- Check that the Expert users (MB, SJW, MN), Maintainers (HM) and Local users are happy with the
+  design decisions
 - H6 M&C loads section
 - H3 Functions mapping
 - H3/4 Timing (1s default, PPS, event message)
@@ -225,7 +226,7 @@ Open issues:
 - Update RadioHDL docs
 - Write RadioHDL article
 - Write HDL RL=0 article - desp_hdl_design_article.txt
-
+- XST : SNR = 1 per visibility for 10000 samples, brigthtest sourcre log 19.5 --> 4.5 dB --> T_int = 1 s is ok.
 
 
 

boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg

@@ -7,7 +7,7 @@ hdl_lib_technology = ip_stratixiv
 synth_files =
     # Commented unb1_bn_capture.vhd and SOPC because only the node is reused.
     # The SOPC causes a simulation error if it not there, because it is instantiated as an entity
-    #$HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
+    #$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
     src/vhdl/unb1_bn_capture_pkg.vhd
     src/vhdl/unb1_bn_capture_input.vhd
     src/vhdl/node_unb1_bn_capture.vhd
@@ -41,7 +41,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_bn_capture_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
     src/vhdl/node_unb1_bn_terminal_bg.vhd
     src/vhdl/unb1_bn_terminal_bg.vhd
     
@@ -31,7 +31,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_bn_terminal_bg_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
     src/vhdl/node_unb1_ddr3.vhd
     src/vhdl/mmm_unb1_ddr3.vhd
     src/vhdl/unb1_ddr3.vhd
@@ -31,7 +31,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
 
 quartus_tcl_files =
     quartus/unb1_ddr3_pins.tcl

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
     $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
     
 

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
     $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
     
 

boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
     src/vhdl/mmm_unb1_ddr3_transpose.vhd
     src/vhdl/unb1_ddr3_transpose.vhd
     
@@ -38,8 +38,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 

boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
     src/vhdl/mmm_unb1_fn_terminal_db.vhd
     src/vhdl/unb1_fn_terminal_db.vhd
     
@@ -30,7 +30,7 @@ quartus_tcl_files =
     quartus/unb1_fn_terminal_db_pins.tcl
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC

boards/uniboard1/designs/unb1_heater/hdllib.cfg

@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS

boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt

@@ -37,7 +37,7 @@ run: rm -rf ~/svn/UniBoard_FP7/RadioHDL/trunk/build/*
         ../../quartus/qsys_unb1_minimal.qsys .
 
     quartus_qip_files =
-        $HDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+        $RADIOHDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 11. For future compilations the file qsys_unb1_minimal.qsys
     (after SOPC->QSYS it is this file: ~/RadioHDL/trunk/build/quartus/unb1_minimal/sopc_unb1_minimal.qsys)

boards/uniboard1/designs/unb1_minimal/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
     src/vhdl/qsys_unb1_minimal_pkg.vhd
     src/vhdl/mmm_unb1_minimal.vhd
     src/vhdl/unb1_minimal.vhd

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg

@@ -32,7 +32,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg

@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg

@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files =
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS