Merge branch 'master' of git.astron.nl:desp/hdl

libraries/io/remu/remu.peripheral.yaml

@@ -8,70 +8,59 @@ hdl_library_description: " This is the description for the remu package "
 peripherals:
  
   # peripheral, remu_reg
-  - 
-    peripheral_name: remu_reg
+  - peripheral_name: remu
 
     parameters:
       - { name: g_data_w, value: 24 }
 
     slave_ports:
-      - 
         # actual hdl name: reg_remu
-        slave_prefix : WORK
-        slave_name   : REMU
-        slave_postfix: REG
+      - slave_name   : REMU
         slave_type   : REG
         fields:
-          -
-            field_name    : reconfigure_key
+          - - field_name    : reconfigure_key
               width         : c_word_w
               access_mode   : WO
               address_offset: 0x0
               field_description: " reconfigure key for safety "
         
-          -
-            field_name    : param
+          - - field_name    : param
               width         : 3
               access_mode   : WO
-            address_offset: 0x1
+              address_offset: 0x4
               radix         : unsigned 
               field_description: " "
         
-          -
-            field_name    : read_param
+          - - field_name    : read_param
               width         : 1
               access_mode   : WO
               side_effect   : PW
-            address_offset: 0x2
+              address_offset: 0x8
               field_description: " read_param "
 
-          -
-            field_name    : write_param
+          - - field_name    : write_param
               width         : 1
               access_mode   : WO
               side_effect   : PW
-            address_offset: 0x3
+              address_offset: 0xc
               field_description: " write_param "
 
-          -
-            field_name    : data_out
+          - - field_name    : data_out
               width         : g_data_w
               access_mode   : RO
-            address_offset: 0x4
+              address_offset: 0x10
               field_description: " data_out "
 
-          -
-            field_name    : data_in
+          - - field_name    : data_in
               width         : g_data_w
               access_mode   : WO
-            address_offset: 0x5
+              address_offset: 0x14
               field_description: " data_in "
 
-          -
-            field_name    : busy
+          - - field_name    : busy
               width         : 1
               access_mode   : RO
-            address_offset: 0x6
+              address_offset: 0x18
               field_description: " busy "
 
         slave_description:  " Remote Upgrade "

libraries/technology/ddr/tech_ddr_component_pkg.vhd

@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
   
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
   PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
   PORT (
     pll_ref_clk                	: IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
   -- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
   COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
   PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+  -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
   COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
   PORT (
     pll_ref_clk                : IN    STD_LOGIC;                       --  pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e3sge3
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
   -- ip_arria10_e1sg
   ------------------------------------------------------------------------------
   
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
@@ -567,7 +567,7 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
-  -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
   PORT (
     amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n

libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd

@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
   ------------------------------------------------------------------------------
   
   -- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
-  -- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+  -- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
  
   COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
   GENERIC (

libraries/technology/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology =
 
 synth_files =
     technology_pkg.vhd
-    $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 
 test_bench_files =
 
@@ -16,10 +16,10 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
-    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
 
 
 
 [quartus_project_file]
 quartus_copy_files =
-    technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+    technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd

libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl

@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/complex_mult/compile_ip.tcl

@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/ddio/compile_ip.tcl

@@ -26,7 +26,7 @@ set IPMODEL "SIM";
 if {$IPMODEL=="PHY"} {
 
     # This file is based on Qsys-generated file msim_setup.tcl.
-    set IP_DIR "$env(HDL_BUILD_DIR)/"
+    set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
         
     #vlib ./work/         ;# Assume library work already exists
     vmap ip_arria10_ddio_in_1_altera_gpio_core_150  ./work/

libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl

@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl

@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {

libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl

@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl

@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {

libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl

@@ -25,7 +25,7 @@
 # - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
 # - replace QSYS_SIMDIR by IP_DIR
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl

@@ -22,7 +22,7 @@
 
 # This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
 
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 # Copy ROM/RAM files to simulation directory
 if {[file isdirectory $IP_DIR]} {

libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl

@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
 

libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl

@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 vmap ip_arria10_remote_update_altera_remote_update_core_150  ./work/
 vmap ip_arria10_remote_update_altera_remote_update_150       ./work/

libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl

@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl

@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/mac_10g/compile_ip.tcl

@@ -26,8 +26,8 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
-set IP_TBDIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists
 

libraries/technology/ip_arria10/mac_10g/hdllib.cfg

@@ -9,7 +9,7 @@ synth_files =
 test_bench_files = 
     # The generated testbench is listed here to create a simulation configuration for it. However
     # the tb is commented because it is not useful, see generate_ip.sh.
-    #$HDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
+    #$RADIOHDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
 
 
 [modelsim_project_file]

libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl

@@ -26,7 +26,7 @@
 # - replace QSYS_SIMDIR by IP_DIR
 # - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
 
-set IP_DIR   "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
 
 #vlib ./work/         ;# Assume library work already exists