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Commit 40f5c430 authored by Eric Kooistra's avatar Eric Kooistra
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Use 'tech_tse' instead of only 'tse' in item names from tech_tse_pkg.vhd and tb_tech_tse_pkg.vhd.

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libraries/io/eth/src/vhdl/avs_eth.vhd
+ 2
− 2
View file @ 40f5c430
......@@ -42,7 +42,7 @@ ENTITY avs_eth IS
---------------------------------------------------------------------------
-- TSE MAC
-- . MOSI
mms_tse_address : IN STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
mms_tse_address : IN STD_LOGIC_VECTOR(c_tech_tse_byte_addr_w-1 DOWNTO 0);
mms_tse_write : IN STD_LOGIC;
mms_tse_read : IN STD_LOGIC;
mms_tse_writedata : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
......@@ -109,7 +109,7 @@ ARCHITECTURE wrap OF avs_eth IS
SIGNAL ram_sla_out : t_mem_miso;
-- LED interface
SIGNAL tse_led : t_tse_led;
SIGNAL tse_led : t_tech_tse_led;
BEGIN
......
libraries/io/eth/src/vhdl/avs_eth_coe.vhd
+ 2
− 2
View file @ 40f5c430
......@@ -42,7 +42,7 @@ ENTITY avs_eth_coe IS
csi_mm_clk : IN STD_LOGIC;
-- TSE MAC
mms_tse_address : IN STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
mms_tse_address : IN STD_LOGIC_VECTOR(c_tech_tse_byte_addr_w-1 DOWNTO 0);
mms_tse_write : IN STD_LOGIC;
mms_tse_read : IN STD_LOGIC;
mms_tse_writedata : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
......@@ -74,7 +74,7 @@ ENTITY avs_eth_coe IS
coe_clk_export : OUT STD_LOGIC;
-- TSE MAC
coe_tse_address_export : OUT STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
coe_tse_address_export : OUT STD_LOGIC_VECTOR(c_tech_tse_byte_addr_w-1 DOWNTO 0);
coe_tse_write_export : OUT STD_LOGIC;
coe_tse_read_export : OUT STD_LOGIC;
coe_tse_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
......
libraries/io/eth/src/vhdl/eth.vhd
+ 5
− 5
View file @ 40f5c430
......@@ -76,7 +76,7 @@ ENTITY eth IS
eth_rxp : IN STD_LOGIC;
-- LED interface
tse_led : OUT t_tse_led
tse_led : OUT t_tech_tse_led
);
END eth;
......@@ -178,13 +178,13 @@ ARCHITECTURE str OF eth IS
SIGNAL tse_tx_siso : t_dp_siso;
SIGNAL tse_tx_sosi : t_dp_sosi;
-- . MAC specific
SIGNAL tse_tx_mac_in : t_tse_tx_mac;
SIGNAL tse_tx_mac_out : t_tse_tx_mac;
SIGNAL tse_tx_mac_in : t_tech_tse_tx_mac;
SIGNAL tse_tx_mac_out : t_tech_tse_tx_mac;
-- . MAC Receive Stream
SIGNAL tse_rx_sosi : t_dp_sosi;
SIGNAL tse_rx_siso : t_dp_siso;
-- . MAC specific
SIGNAL tse_rx_mac_out : t_tse_rx_mac;
SIGNAL tse_rx_mac_out : t_tech_tse_rx_mac;
BEGIN
......@@ -277,7 +277,7 @@ BEGIN
clk => st_clk,
-- Streaming Sink
snk_in_err => rx_adapt_sosi.err(c_tse_error_w-1 DOWNTO 0), -- preserve error field from TSE MAC stream
snk_in_err => rx_adapt_sosi.err(c_tech_tse_error_w-1 DOWNTO 0), -- preserve error field from TSE MAC stream
snk_in => rx_adapt_sosi,
snk_out => rx_adapt_siso,
......
libraries/io/eth/src/vhdl/eth_pkg.vhd
+ 5
− 5
View file @ 40f5c430
......@@ -31,12 +31,12 @@ USE tech_tse_lib.tech_tse_pkg.ALL;
PACKAGE eth_pkg IS
CONSTANT c_eth_data_w : NATURAL := c_tse_data_w; -- = c_word_w
CONSTANT c_eth_empty_w : NATURAL := c_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
CONSTANT c_eth_error_w : NATURAL := c_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
CONSTANT c_eth_data_w : NATURAL := c_tech_tse_data_w; -- = c_word_w
CONSTANT c_eth_empty_w : NATURAL := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
CONSTANT c_eth_error_w : NATURAL := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
CONSTANT c_eth_rx_ready_latency : NATURAL := c_tse_rx_ready_latency; -- = 2 = default when FIFO is used
CONSTANT c_eth_tx_ready_latency : NATURAL := c_tse_tx_ready_latency; -- = 0, c_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
CONSTANT c_eth_rx_ready_latency : NATURAL := c_tech_tse_rx_ready_latency; -- = 2 = default when FIFO is used
CONSTANT c_eth_tx_ready_latency : NATURAL := c_tech_tse_tx_ready_latency; -- = 0, c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
CONSTANT c_eth_ready_latency : NATURAL := 1; -- = 1, fixed ETH module internal RL
-- Maximum feasible frame size
......
libraries/io/eth/tb/vhdl/tb_eth.vhd
+ 37
− 37
View file @ 40f5c430
......@@ -33,7 +33,7 @@
-- ------- -------
--
-- The tb is self checking based on:
-- . proc_tse_rx_packet() for expected header and data type
-- . proc_tech_tse_rx_packet() for expected header and data type
-- . tx_pkt_cnt=rx_pkt_cnt > 0 must be true at the tb_end.
-- Usage:
-- > as 10
......@@ -57,12 +57,12 @@ USE tech_tse_lib.tb_tech_tse_pkg.ALL;
ENTITY tb_eth IS
-- Test bench control parameters
GENERIC (
-- g_data_type = c_tb_tse_data_type_symbols = 0
-- g_data_type = c_tb_tse_data_type_counter = 1
-- g_data_type = c_tb_tse_data_type_arp = 2
-- g_data_type = c_tb_tse_data_type_ping = 3
-- g_data_type = c_tb_tse_data_type_udp = 4
g_data_type : NATURAL := c_tb_tse_data_type_udp
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
-- g_data_type = c_tb_tech_tse_data_type_arp = 2
-- g_data_type = c_tb_tech_tse_data_type_ping = 3
-- g_data_type = c_tb_tech_tse_data_type_udp = 4
g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
);
END tb_eth;
......@@ -78,7 +78,7 @@ ARCHITECTURE tb OF tb_eth IS
-- TSE constants
CONSTANT c_promis_en : BOOLEAN := FALSE;
CONSTANT c_tx_ready_latency : NATURAL := c_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tse_tx_ready_latency
CONSTANT c_tx_ready_latency : NATURAL := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
-- Payload user data
......@@ -94,7 +94,7 @@ ARCHITECTURE tb OF tb_eth IS
CONSTANT c_dut_src_mac_hi : NATURAL := TO_UINT(c_dut_src_mac(c_network_eth_mac_addr_w-1 DOWNTO c_word_w));
CONSTANT c_dut_src_mac_lo : NATURAL := TO_UINT(c_dut_src_mac( c_word_w-1 DOWNTO 0));
-- support only ARP and IPv4 over ETH
CONSTANT c_dut_ethertype : NATURAL := sel_a_b(g_data_type-c_tb_tse_data_type_arp, c_network_eth_type_ip, c_network_eth_type_arp);
CONSTANT c_dut_ethertype : NATURAL := sel_a_b(g_data_type-c_tb_tech_tse_data_type_arp, c_network_eth_type_ip, c_network_eth_type_arp);
CONSTANT c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
src_mac => c_lcu_src_mac,
eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
......@@ -106,7 +106,7 @@ ARCHITECTURE tb OF tb_eth IS
CONSTANT c_lcu_ip_addr : NATURAL := 16#05060708#; -- = 05:06:07:08
CONSTANT c_dut_ip_addr : NATURAL := 16#01020304#;
CONSTANT c_tb_ip_total_length : NATURAL := c_network_ip_total_length + c_tb_ip_nof_data;
CONSTANT c_tb_ip_protocol : NATURAL := sel_a_b(g_data_type-c_tb_tse_data_type_ping, c_network_ip_protocol_udp, c_network_ip_protocol_icmp); -- support only ping protocol or UDP protocol over IP
CONSTANT c_tb_ip_protocol : NATURAL := sel_a_b(g_data_type-c_tb_tech_tse_data_type_ping, c_network_ip_protocol_udp, c_network_ip_protocol_icmp); -- support only ping protocol or UDP protocol over IP
CONSTANT c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
......@@ -210,7 +210,7 @@ ARCHITECTURE tb OF tb_eth IS
SIGNAL eth_psc_access : STD_LOGIC;
SIGNAL eth_txp : STD_LOGIC;
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL eth_led : t_tse_led;
SIGNAL eth_led : t_tech_tse_led;
-- ETH MM registers interface
SIGNAL eth_reg_miso : t_mem_miso;
......@@ -238,14 +238,14 @@ ARCHITECTURE tb OF tb_eth IS
SIGNAL lcu_tx_en : STD_LOGIC := '1';
SIGNAL lcu_tx_siso : t_dp_siso;
SIGNAL lcu_tx_sosi : t_dp_sosi;
SIGNAL lcu_tx_mac_in : t_tse_tx_mac;
SIGNAL lcu_tx_mac_out : t_tse_tx_mac;
SIGNAL lcu_tx_mac_in : t_tech_tse_tx_mac;
SIGNAL lcu_tx_mac_out : t_tech_tse_tx_mac;
SIGNAL lcu_rx_sosi : t_dp_sosi;
SIGNAL lcu_rx_siso : t_dp_siso;
SIGNAL lcu_rx_mac_out : t_tse_rx_mac;
SIGNAL lcu_rx_mac_out : t_tech_tse_rx_mac;
SIGNAL lcu_txp : STD_LOGIC;
SIGNAL lcu_rxp : STD_LOGIC;
SIGNAL lcu_led : t_tse_led;
SIGNAL lcu_led : t_tech_tse_led;
-- Verification
SIGNAL tx_pkt_cnt : NATURAL := 0;
......@@ -298,7 +298,7 @@ BEGIN
-- Wait for ETH init
WHILE dut_eth_init='1' LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
-- Setup the TSE MAC
proc_tse_setup(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_dut_src_mac, eth_psc_access,
mm_clk, eth_tse_miso, eth_tse_mosi);
dut_tse_init <= '0';
......@@ -369,7 +369,7 @@ BEGIN
-- write control register to enable tx
IF c_tb_reply_payload=TRUE THEN
-- . copy the received payload to the response payload (overwrite part of the default response header in case of raw ETH)
FOR I IN func_tb_tse_header_size(g_data_type) TO TO_UINT(eth_mm_reg_control.tx_nof_words)-1 LOOP
FOR I IN func_tech_tse_header_size(g_data_type) TO TO_UINT(eth_mm_reg_control.tx_nof_words)-1 LOOP
proc_mem_mm_bus_rd(c_eth_ram_rx_offset+I, mm_clk, eth_ram_miso, eth_ram_mosi);
proc_mem_mm_bus_rd_latency(c_mem_ram_rd_latency, mm_clk);
proc_mem_mm_bus_wr(c_eth_ram_tx_offset+I, TO_SINT(eth_ram_miso.rddata(c_word_w-1 DOWNTO 0)), mm_clk, eth_ram_miso, eth_ram_mosi);
......@@ -399,7 +399,7 @@ BEGIN
-- Wait for reset release
WHILE mm_rst='1' LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
-- Setup the LCU TSE MAC
proc_tse_setup(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_lcu_src_mac, lcu_psc_access,
mm_clk, lcu_tse_miso, lcu_tse_mosi);
-- Wait for DUT init done
......@@ -423,22 +423,22 @@ BEGIN
WHILE lcu_init/='0' LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
-- proc_tse_tx_packet(tx_total_header, 100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
FOR I IN 0 TO 40 LOOP
proc_tse_tx_packet(tx_total_header, I, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
proc_tech_tse_tx_packet(tx_total_header, I, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--FOR J IN 0 TO 9 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
END LOOP;
-- proc_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
-- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
FOR I IN 0 TO 1500 * 5 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
tb_end <= '1';
......@@ -455,12 +455,12 @@ BEGIN
-- Verification of multiple rx packets is only supported when all packets
-- are of the same g_data_type, because the rx process can only support
-- one expected result. The proc_tse_rx_packet does not (yet) interpret the
-- one expected result. The proc_tech_tse_rx_packet does not (yet) interpret the
-- actually received packet, it relies on the preset expected total_header.
-- Receive forever
WHILE TRUE LOOP
proc_tse_rx_packet(exp_total_header, g_data_type, st_clk, lcu_rx_sosi, lcu_rx_siso);
proc_tech_tse_rx_packet(exp_total_header, g_data_type, st_clk, lcu_rx_sosi, lcu_rx_siso);
END LOOP;
WAIT;
......
libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+ 5
− 5
View file @ 40f5c430
......@@ -88,7 +88,7 @@ ARCHITECTURE tb OF tb_eth_udp_offload IS
CONSTANT c_lcu_ip_addr : NATURAL := 16#05060708#; -- = 05:06:07:08
CONSTANT c_dut_ip_addr : NATURAL := 16#01020304#;
CONSTANT c_tb_ip_total_length : NATURAL := c_network_ip_total_length + c_tb_ip_nof_data;
CONSTANT c_tb_ip_protocol : NATURAL := c_network_ip_protocol_udp; --sel_a_b(g_data_type-c_tb_tse_data_type_ping, c_network_ip_protocol_udp, c_network_ip_protocol_icmp); -- support only ping protocol or UDP protocol over IP
CONSTANT c_tb_ip_protocol : NATURAL := c_network_ip_protocol_udp; --sel_a_b(g_data_type-c_tb_tech_tse_data_type_ping, c_network_ip_protocol_udp, c_network_ip_protocol_icmp); -- support only ping protocol or UDP protocol over IP
CONSTANT c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
......@@ -143,7 +143,7 @@ ARCHITECTURE tb OF tb_eth_udp_offload IS
-- TSE constants
CONSTANT c_promis_en : BOOLEAN := FALSE;
CONSTANT c_tx_ready_latency : NATURAL := c_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tse_tx_ready_latency
CONSTANT c_tx_ready_latency : NATURAL := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
-- ETH control
CONSTANT c_dut_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
......@@ -258,7 +258,7 @@ BEGIN
-- Wait for ETH init
WHILE dut_eth_init='1' LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
-- Setup the TSE MAC
proc_tse_setup(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_dut_src_mac, eth_psc_access,
mm_clk, eth_tse_miso, eth_tse_mosi);
dut_tse_init <= '0';
......
libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+ 5
− 5
View file @ 40f5c430
......@@ -42,10 +42,10 @@ BEGIN
-- Try ETH settings : GENERIC MAP (g_data_type => )
u_use_symbols : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_symbols);
u_use_counter : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_counter);
u_use_arp : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_arp );
u_use_ping : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_ping );
u_use_udp : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_udp );
u_use_symbols : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_symbols);
u_use_counter : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_counter);
u_use_arp : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_arp );
u_use_ping : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_ping );
u_use_udp : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_udp );
END tb;
libraries/technology/tse/tb_tech_tse.vhd
+ 33
− 33
View file @ 40f5c430
......@@ -22,7 +22,7 @@
-- Purpose: Testbench for tech_tse the Tripple Speed Ethernet IP technology wrapper.
-- Description:
-- The tb is self checking based on:
-- . proc_tse_rx_packet() for expected header and data type
-- . proc_tech_tse_rx_packet() for expected header and data type
-- . tx_pkt_cnt=rx_pkt_cnt > 0 must be true at the tb_end.
-- Usage:
-- > as 10
......@@ -44,9 +44,9 @@ USE WORK.tb_tech_tse_pkg.ALL;
ENTITY tb_tech_tse IS
-- Test bench control parameters
GENERIC (
-- g_data_type = c_tb_tse_data_type_symbols = 0
-- g_data_type = c_tb_tse_data_type_counter = 1
g_data_type : NATURAL := c_tb_tse_data_type_symbols
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols
);
END tb_tech_tse;
......@@ -61,7 +61,7 @@ ARCHITECTURE tb OF tb_tech_tse IS
CONSTANT cable_delay : TIME := 12 ns;
CONSTANT c_promis_en : BOOLEAN := FALSE;
CONSTANT c_tx_ready_latency : NATURAL := c_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tse_tx_ready_latency
CONSTANT c_tx_ready_latency : NATURAL := c_tech_tse_tx_ready_latency; -- 0, 1 are supported, must match TSE MAC c_tech_tse_tx_ready_latency
CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
CONSTANT c_dst_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"10FA01020300";
......@@ -97,21 +97,21 @@ ARCHITECTURE tb OF tb_tech_tse IS
SIGNAL tx_siso : t_dp_siso;
SIGNAL tx_sosi : t_dp_sosi;
-- . MAC specific
SIGNAL tx_mac_in : t_tse_tx_mac;
SIGNAL tx_mac_out : t_tse_tx_mac;
SIGNAL tx_mac_in : t_tech_tse_tx_mac;
SIGNAL tx_mac_out : t_tech_tse_tx_mac;
-- TSE MAC receive interface
-- . The tb is the ST sink
SIGNAL rx_sosi : t_dp_sosi;
SIGNAL rx_siso : t_dp_siso;
-- . MAC specific
SIGNAL rx_mac_out : t_tse_rx_mac;
SIGNAL rx_mac_out : t_tech_tse_rx_mac;
-- TSE PHY interface
SIGNAL eth_txp : STD_LOGIC;
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL tse_led : t_tse_led;
SIGNAL tse_led : t_tech_tse_led;
-- Verification
SIGNAL tx_pkt_cnt : NATURAL := 0;
......@@ -143,7 +143,7 @@ BEGIN
mm_rst <= '0';
FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
proc_tse_setup(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_src_mac, mm_psc_access,
mm_clk, mm_miso, mm_mosi);
mm_init <= '0';
......@@ -175,28 +175,28 @@ BEGIN
-- . For I=1 to 46 the payload length remains 46 with padding zeros, so empty = 2
-- . For I>46 the payload length is I and empty = 4 - (I mod 4)
-- proc_tse_tx_packet(total_header_etherlen, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_etherlen, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
FOR I IN 0 TO 59 LOOP
proc_tse_tx_packet(total_header_loopback, I, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
proc_tech_tse_tx_packet(total_header_loopback, I, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
END LOOP;
-- proc_tse_tx_packet(total_header_loopback, 100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1499, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi); -- verify st empty
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tse_tx_packet(total_header_loopback, 1501, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi); -- verify c_eth_payload_max
-- proc_tse_tx_packet(total_header_loopback, 100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1499, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi); -- verify st empty
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
-- proc_tech_tse_tx_packet(total_header_loopback, 1501, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi); -- verify c_eth_payload_max
-- proc_tech_tse_tx_packet(total_header_loopback, 100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
FOR I IN 0 TO 1500 * 2 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
tb_end <= '1';
......@@ -215,7 +215,7 @@ BEGIN
-- Receive forever
WHILE TRUE LOOP
proc_tse_rx_packet(total_header_loopback, g_data_type, st_clk, rx_sosi, rx_siso);
proc_tech_tse_rx_packet(total_header_loopback, g_data_type, st_clk, rx_sosi, rx_siso);
END LOOP;
WAIT;
......
libraries/technology/tse/tb_tech_tse_pkg.vhd
+ 109
− 112
View file @ 40f5c430
This diff is collapsed.
libraries/technology/tse/tech_tse.vhd
+ 4
− 4
View file @ 40f5c430
......@@ -55,21 +55,21 @@ ENTITY tech_tse IS
tx_snk_in : IN t_dp_sosi;
tx_snk_out : OUT t_dp_siso;
-- . MAC specific
tx_mac_in : IN t_tse_tx_mac;
tx_mac_out : OUT t_tse_tx_mac;
tx_mac_in : IN t_tech_tse_tx_mac;
tx_mac_out : OUT t_tech_tse_tx_mac;
-- MAC receive interface
-- . ST Source
rx_src_in : IN t_dp_siso;
rx_src_out : OUT t_dp_sosi;
-- . MAC specific
rx_mac_out : OUT t_tse_rx_mac;
rx_mac_out : OUT t_tech_tse_rx_mac;
-- PHY interface
eth_txp : OUT STD_LOGIC;
eth_rxp : IN STD_LOGIC;
tse_led : OUT t_tse_led
tse_led : OUT t_tech_tse_led
);
END tech_tse;
......
libraries/technology/tse/tech_tse_pkg.vhd
+ 26
− 26
View file @ 40f5c430
......@@ -26,34 +26,34 @@ USE common_lib.common_pkg.ALL;
PACKAGE tech_tse_pkg IS
CONSTANT c_tse_reg_addr_w : NATURAL := 8; -- = max 256 MAC registers
CONSTANT c_tse_byte_addr_w : NATURAL := c_tse_reg_addr_w + 2;
CONSTANT c_tse_byte_addr_pcs_offset : NATURAL := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
CONSTANT c_tse_data_w : NATURAL := c_word_w; -- = 32
CONSTANT c_tech_tse_reg_addr_w : NATURAL := 8; -- = max 256 MAC registers
CONSTANT c_tech_tse_byte_addr_w : NATURAL := c_tech_tse_reg_addr_w + 2;
CONSTANT c_tech_tse_byte_addr_pcs_offset : NATURAL := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
CONSTANT c_tech_tse_data_w : NATURAL := c_word_w; -- = 32
CONSTANT c_tse_symbol_w : NATURAL := c_byte_w; -- = 8
CONSTANT c_tse_symbol_max : NATURAL := 2**c_tse_symbol_w-1; -- = 255
CONSTANT c_tse_symbols_per_beat : NATURAL := c_tse_data_w / c_tse_symbol_w; -- = 4
CONSTANT c_tech_tse_symbol_w : NATURAL := c_byte_w; -- = 8
CONSTANT c_tech_tse_symbol_max : NATURAL := 2**c_tech_tse_symbol_w-1; -- = 255
CONSTANT c_tech_tse_symbols_per_beat : NATURAL := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
CONSTANT c_tse_pcs_reg_addr_w : NATURAL := 5; -- = max 32 PCS registers
CONSTANT c_tse_pcs_halfword_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
CONSTANT c_tse_pcs_byte_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 2;
CONSTANT c_tse_pcs_data_w : NATURAL := c_halfword_w; -- = 16;
CONSTANT c_tech_tse_pcs_reg_addr_w : NATURAL := 5; -- = max 32 PCS registers
CONSTANT c_tech_tse_pcs_halfword_addr_w : NATURAL := c_tech_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
CONSTANT c_tech_tse_pcs_byte_addr_w : NATURAL := c_tech_tse_pcs_reg_addr_w + 2;
CONSTANT c_tech_tse_pcs_data_w : NATURAL := c_halfword_w; -- = 16;
CONSTANT c_tse_empty_w : NATURAL := 2;
CONSTANT c_tse_tx_error_w : NATURAL := 1;
CONSTANT c_tse_rx_error_w : NATURAL := 6;
CONSTANT c_tse_error_w : NATURAL := largest(c_tse_tx_error_w, c_tse_rx_error_w);
CONSTANT c_tse_err_stat_w : NATURAL := 18;
CONSTANT c_tse_frm_type_w : NATURAL := 4;
CONSTANT c_tech_tse_empty_w : NATURAL := 2;
CONSTANT c_tech_tse_tx_error_w : NATURAL := 1;
CONSTANT c_tech_tse_rx_error_w : NATURAL := 6;
CONSTANT c_tech_tse_error_w : NATURAL := largest(c_tech_tse_tx_error_w, c_tech_tse_rx_error_w);
CONSTANT c_tech_tse_err_stat_w : NATURAL := 18;
CONSTANT c_tech_tse_frm_type_w : NATURAL := 4;
CONSTANT c_tse_rx_ready_latency : NATURAL := 2; -- 2 = default when FIFO is used
CONSTANT c_tse_tx_ready_latency : NATURAL := 1; -- c_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
CONSTANT c_tech_tse_rx_ready_latency : NATURAL := 2; -- 2 = default when FIFO is used
CONSTANT c_tech_tse_tx_ready_latency : NATURAL := 1; -- c_tech_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
CONSTANT c_tse_tx_fifo_depth : NATURAL := 256; -- nof words for Tx FIFO
CONSTANT c_tse_rx_fifo_depth : NATURAL := 256; -- nof words for Rx FIFO
CONSTANT c_tech_tse_tx_fifo_depth : NATURAL := 256; -- nof words for Tx FIFO
CONSTANT c_tech_tse_rx_fifo_depth : NATURAL := 256; -- nof words for Rx FIFO
TYPE t_tse_tx_mac IS RECORD
TYPE t_tech_tse_tx_mac IS RECORD
-- Tx MAC inputs
crc_fwd : STD_LOGIC;
-- Tx MAC outputs
......@@ -63,17 +63,17 @@ PACKAGE tech_tse_pkg IS
uflow : STD_LOGIC;
END RECORD;
TYPE t_tse_rx_mac IS RECORD
TYPE t_tech_tse_rx_mac IS RECORD
-- Rx MAC inputs
-- Rx MAC outputs
ethertype: STD_LOGIC_VECTOR(c_tse_err_stat_w-1 DOWNTO 0);
frm_type : STD_LOGIC_VECTOR(c_tse_frm_type_w-1 DOWNTO 0);
ethertype: STD_LOGIC_VECTOR(c_tech_tse_err_stat_w-1 DOWNTO 0);
frm_type : STD_LOGIC_VECTOR(c_tech_tse_frm_type_w-1 DOWNTO 0);
dsav : STD_LOGIC;
a_full : STD_LOGIC;
a_empty : STD_LOGIC;
END RECORD;
TYPE t_tse_led IS RECORD
TYPE t_tech_tse_led IS RECORD
an : STD_LOGIC;
link : STD_LOGIC;
disp_err : STD_LOGIC;
......
libraries/technology/tse/tech_tse_stratixiv.vhd
+ 30
− 30
View file @ 40f5c430
......@@ -55,27 +55,27 @@ ENTITY tech_tse_stratixiv IS
tx_snk_in : IN t_dp_sosi;
tx_snk_out : OUT t_dp_siso;
-- . MAC specific
tx_mac_in : IN t_tse_tx_mac;
tx_mac_out : OUT t_tse_tx_mac;
tx_mac_in : IN t_tech_tse_tx_mac;
tx_mac_out : OUT t_tech_tse_tx_mac;
-- MAC receive interface
-- . ST Source
rx_src_in : IN t_dp_siso;
rx_src_out : OUT t_dp_sosi;
-- . MAC specific
rx_mac_out : OUT t_tse_rx_mac;
rx_mac_out : OUT t_tech_tse_rx_mac;
-- PHY interface
eth_txp : OUT STD_LOGIC;
eth_rxp : IN STD_LOGIC;
tse_led : OUT t_tse_led
tse_led : OUT t_tech_tse_led
);
END tech_tse_stratixiv;
ARCHITECTURE str OF tech_tse_stratixiv IS
SIGNAL ff_tx_mod : STD_LOGIC_VECTOR(c_tse_empty_w-1 DOWNTO 0);
SIGNAL ff_tx_mod : STD_LOGIC_VECTOR(c_tech_tse_empty_w-1 DOWNTO 0);
SIGNAL ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
......@@ -91,7 +91,7 @@ BEGIN
tx_snk_out.xon <= '1';
-- Force empty = 0 when eop = '0' to avoid TSE MAC bug of missing two bytes when empty = 2
ff_tx_mod <= tx_snk_in.empty(c_tse_empty_w-1 DOWNTO 0) WHEN tx_snk_in.eop='1' ELSE (OTHERS=>'0');
ff_tx_mod <= tx_snk_in.empty(c_tech_tse_empty_w-1 DOWNTO 0) WHEN tx_snk_in.eop='1' ELSE (OTHERS=>'0');
-- Force unused bits and fields in rx_src_out to c_dp_sosi_rst to avoid confusing 'X' in wave window
rx_src_out <= ff_rx_out;
......@@ -112,7 +112,7 @@ BEGIN
-- . Avalon ST
ff_tx_clk => tx_snk_clk,
ff_tx_rdy => tx_snk_out.ready,
ff_tx_data => tx_snk_in.data(c_tse_data_w-1 DOWNTO 0),
ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
ff_tx_wren => tx_snk_in.valid,
ff_tx_sop => tx_snk_in.sop,
ff_tx_eop => tx_snk_in.eop,
......@@ -128,12 +128,12 @@ BEGIN
-- . Avalon ST
ff_rx_clk => rx_src_clk,
ff_rx_rdy => rx_src_in.ready,
ff_rx_data => ff_rx_out.data(c_tse_data_w-1 DOWNTO 0),
ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
ff_rx_dval => ff_rx_out.valid,
ff_rx_sop => ff_rx_out.sop,
ff_rx_eop => ff_rx_out.eop,
ff_rx_mod => ff_rx_out.empty(c_tse_empty_w-1 DOWNTO 0),
rx_err => ff_rx_out.err(c_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
-- [4] PHY error on GMII
-- [3] receive frame truncated due to FIFO overflow
-- [2] CRC-32 error
......@@ -149,10 +149,10 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
address => mm_sla_in.address(c_tse_byte_addr_w-1 DOWNTO 2),
readdata => mm_sla_out.rddata(c_tse_data_w-1 DOWNTO 0),
address => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
readdata => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
read => mm_sla_in.rd,
writedata => mm_sla_in.wrdata(c_tse_data_w-1 DOWNTO 0),
writedata => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
write => mm_sla_in.wr,
waitrequest => mm_sla_out.waitrequest,
-- Status LEDs
......@@ -187,7 +187,7 @@ BEGIN
-- . Avalon ST
ff_tx_clk => tx_snk_clk,
ff_tx_rdy => tx_snk_out.ready,
ff_tx_data => tx_snk_in.data(c_tse_data_w-1 DOWNTO 0),
ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
ff_tx_wren => tx_snk_in.valid,
ff_tx_sop => tx_snk_in.sop,
ff_tx_eop => tx_snk_in.eop,
......@@ -203,12 +203,12 @@ BEGIN
-- . Avalon ST
ff_rx_clk => rx_src_clk,
ff_rx_rdy => rx_src_in.ready,
ff_rx_data => ff_rx_out.data(c_tse_data_w-1 DOWNTO 0),
ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
ff_rx_dval => ff_rx_out.valid,
ff_rx_sop => ff_rx_out.sop,
ff_rx_eop => ff_rx_out.eop,
ff_rx_mod => ff_rx_out.empty(c_tse_empty_w-1 DOWNTO 0),
rx_err => ff_rx_out.err(c_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
-- [4] PHY error on GMII
-- [3] receive frame truncated due to FIFO overflow
-- [2] CRC-32 error
......@@ -224,10 +224,10 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
address => mm_sla_in.address(c_tse_byte_addr_w-1 DOWNTO 2),
readdata => mm_sla_out.rddata(c_tse_data_w-1 DOWNTO 0),
address => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
readdata => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
read => mm_sla_in.rd,
writedata => mm_sla_in.wrdata(c_tse_data_w-1 DOWNTO 0),
writedata => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
write => mm_sla_in.wr,
waitrequest => mm_sla_out.waitrequest,
-- ALTGX_RECONFIG
......
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