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Commit 3e5574e5 authored by Job van Wee's avatar Job van Wee
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1 merge request!215Resolve L2SDP-660
Pipeline #25893 passed
Stage: simulation
Stage: synthesis
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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
+ 12
− 12
View file @ 3e5574e5
......@@ -36,8 +36,8 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddrctrl_repack IS
GENERIC (
g_tech_ddr : t_c_tech_ddr;
g_in_data_w : NATURAL := 168
g_tech_ddr : t_c_tech_ddr; -- type of memory
g_in_data_w : NATURAL := 168 -- the input data with
);
PORT (
clk : IN STD_LOGIC;
......@@ -50,18 +50,18 @@ END ddrctrl_repack;
ARCHITECTURE rtl OF ddrctrl_repack IS
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); --576
CONSTANT k_c_v_w : NATURAL := c_out_data_w*2;
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152
SIGNAL c_v_count : NATURAL := 0;
SIGNAL out_data_count : NATURAL := 0;
SIGNAL c_v_count : NATURAL := 0; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
SIGNAL out_data_count : NATURAL := 0; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
BEGIN
p_clk : PROCESS(clk)
VARIABLE a_of :NATURAL := 0;
VARIABLE c_v : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE a_of : NATURAL := 0; -- amount of overflow
VARIABLE c_v : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0) := (OTHERS => '0'); -- the vector that stores the input data until the data is put into the output data vector
BEGIN
......
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+ 25
− 16
View file @ 3e5574e5
......@@ -37,7 +37,7 @@ ENTITY tb_ddrctrl_repack IS
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
g_in_data_w : NATURAL := 168; -- input data vector with
g_sim_lengt : NATURAL := 32 -- amount of times there wil be input data for ddrctrl_repack in this testbench
g_sim_lengt : NATURAL := 52 -- amount of times there wil be input data for ddrctrl_repack in this testbench
);
END tb_ddrctrl_repack;
......@@ -57,11 +57,13 @@ ARCHITECTURE tb OF tb_ddrctrl_repack IS
END LOOP;
RETURN temp;
END FUNCTION c_total_vector_init;
CONSTANT c_total_vector : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0) := c_total_vector_init; -- vector witch contains all input data vectors to make it easy to fill ctr_vector
CONSTANT c_total_vector : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
SIGNAL total_vector_cnt : NATURAL := 0; -- signal to keep track of how many times there has been checked if there is the correct output
SIGNAL ctr_of : NATURAL := 0; -- signal which contains the amount of overflow for checking
SIGNAL in_data_cnt : NATURAL := 0;
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell when the testing has started
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
SIGNAL clk : STD_LOGIC := '1'; -- clock signal
......@@ -83,15 +85,16 @@ BEGIN
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT UNTIL out_of /= 0; -- wait for out_of /= 0 to align to ddrctrl_repack properly
WAIT UNTIL out_of = 0; -- align to ddrctrl_repack
test_running <= '1'; -- start of test
-- Filling the input vector g_sim_lengt amount of times.
make_in_data : FOR I IN 0 TO g_sim_lengt-1 LOOP
--ASSERT FALSE REPORT "I = " & NATURAL'image(I) SEVERITY NOTE;
in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w);
WAIT FOR c_clk_period*1;
in_data_cnt <= in_data_cnt + 1;
END LOOP;
test_running <= '0';
-- Stop the testbench.
WAIT FOR c_clk_period*5;
......@@ -101,19 +104,25 @@ BEGIN
END PROCESS;
-- Verification by checking if the input vectors are correctly put into the output vector.
-- Verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected.
p_verify : PROCESS
BEGIN
VARIABLE ctr_of : NATURAL := 0;
VARIABLE out_data_cnt : NATURAL := 0;
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT UNTIL out_of /= 0; -- wait for out_of /= 0 to align to ddrctrl_repack properly
WAIT UNTIL out_of = 0; -- align to ddrctrl_repack
WAIT FOR c_clk_period*1; -- first outputdata is empty
BEGIN
IF rising_edge(out_sosi.valid) THEN
ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(total_vector_cnt+1)-1 DOWNTO c_out_data_w*total_vector_cnt) REPORT "Data does not match, total_vector_cnt = " & NATURAL'image(total_vector_cnt) SEVERITY NOTE;
total_vector_cnt <= total_vector_cnt + 1;
WAIT UNTIL rising_edge(out_sosi.valid);
--WAIT FOR c_clk_period*1;
IF test_running = '1' THEN
ASSERT FALSE REPORT "ik werk" SEVERITY NOTE;
IF out_data_cnt mod 2 = 1 THEN
ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*(out_data_cnt+1);
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) SEVERITY ERROR;
END IF;
ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(out_data_cnt+1)-1 DOWNTO c_out_data_w*out_data_cnt) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
out_data_cnt := out_data_cnt + 1;
END IF;
END PROCESS;
......
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