add key to hdllib.cfg

boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg

@@ -45,3 +45,5 @@ quartus_tcl_files =
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+

boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg

@@ -45,3 +45,5 @@ quartus_tcl_files =
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
 
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+

boards/uniboard2b/designs/unb2b_heater/hdllib.cfg

@@ -36,3 +36,5 @@ quartus_vhdl_files =
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
 
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+

boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg

@@ -37,6 +37,5 @@ quartus_vhdl_files =
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
 
-nios2_app_userflags =
-    "use=gen2"
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
 

boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg

@@ -61,3 +61,6 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+

libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg

@@ -36,3 +36,6 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+

libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg

@@ -33,3 +33,6 @@ quartus_tcl_files =
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
 
+
+nios2_app_userflags = -DCOMPILE_FOR_SOPC
+

libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg

@@ -32,3 +32,6 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+

libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg

@@ -30,3 +30,6 @@ quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/s
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
+nios2_app_userflags = -DCOMPILE_FOR_QSYS
+

libraries/io/tr_xaui/hdllib.cfg

@@ -2,7 +2,7 @@ hdl_lib_name = tr_xaui
 hdl_library_clause_name = tr_xaui_lib
 hdl_lib_uses_synth = common dp mdio diagnostics tech_xaui
 hdl_lib_uses_sim = 
-hdl_lib_technology = ip_stratixiv 
+hdl_lib_technology = 
 
 synth_files =
     src/vhdl/tr_xaui_deframer.vhd

libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_clkbuf_global.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_clkbuf_global.qsys
+

libraries/technology/ip_arria10/complex_mult/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_complex_mult.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_complex_mult.qsys
+

libraries/technology/ip_arria10/ddio/hdllib.cfg

@@ -20,3 +20,9 @@ modelsim_compile_ip_files =
 quartus_qip_files =
     generated/ip_arria10_ddio_in_1.qip
     generated/ip_arria10_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_ddio_in_1.qsys
+    ip_arria10_ddio_out_1.qsys
+

libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_ddr4_4g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_ddr4_4g_1600.qsys
+

libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg

@@ -17,3 +17,7 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_ddr4_4g_2000.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_ddr4_4g_2000.qsys

libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_ddr4_8g_2400.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_ddr4_8g_2400.qsys
+

libraries/technology/ip_arria10/fifo/hdllib.cfg

@@ -17,3 +17,10 @@ test_bench_files =
 
 [quartus_project_file]
 
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_fifo_sc.qsys
+    ip_arria10_fifo_dc.qsys
+    ip_arria10_fifo_dc_mixed_widths.qsys
+

libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_asmi_parallel.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_asmi_parallel.qsys
+

libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_remote_update.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_remote_update.qsys
+

libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_fractional_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_fractional_pll_clk125.qsys
+