Use v.busy, instead of r.busy, to allow start_pulse at mm_done, to support...

Use v.busy, instead of r.busy, to allow start_pulse at mm_done, to support zero gaps between output blocks.

libraries/base/dp/src/vhdl/dp_block_from_mm.vhd

@@ -124,7 +124,11 @@ BEGIN
     IF r.busy = '0' AND start_pulse = '1' THEN
       -- initiate next block
       v.busy := '1';
-    ELSIF r.busy = '1' THEN
+    END IF;
+
+    -- use v.busy, instead of r.busy, to allow start_pulse at mm_done, to
+    -- support zero gaps between output blocks
+    IF v.busy = '1' THEN
       IF out_siso.ready = '1' THEN
         -- continue with block
         mm_mosi.rd <= '1';