Verify stream_en_arr via g_disable_stream.

libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd

@@ -19,6 +19,14 @@
 -- Author: Eric Kooistra, 3 Sept 2021
 -- Purpose: Verify dp_bsn_align_v2
 -- Description:
+--   The tb verifies:
+--   . DUT alignment of g_nof_streams
+--   . DUT restart via g_tb_nof_restart > 1
+--   . gaps or no gaps between blocks via g_block_period >= g_block_size
+--   . g_bsn_latency_max in combination with g_tb_diff_delay_max
+--   . g_use_mm_output using DUT MM to DP or external MM to DP in tb
+--   . g_replacement_value for a remote g_disable_stream (one is enough
+--     to verify), the local stream cannot be disabled.
 -- Usage:
 -- > as 10
 -- > run -all
@@ -45,6 +53,7 @@ ENTITY tb_dp_bsn_align_v2 IS
     g_bsn_w                : NATURAL := c_dp_stream_bsn_w;  -- number of bits in sosi BSN
     g_data_w               : NATURAL := 16;     -- number of bits in sosi data
     g_replacement_value    : INTEGER := 17;      -- output sosi data replacement value for missing input blocks
+    g_disable_stream       : NATURAL := 1;      -- default 0 to enable all streams, > 0 selects stream that will be disabled
     g_use_mm_output        : BOOLEAN := FALSE;   -- output via MM or via streaming DP
     g_pipeline_input       : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure
     g_rd_latency           : NATURAL := 2;      -- 1 or 2, choose 2 to ease timing closure
@@ -96,14 +105,16 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS
   SIGNAL tb_end                : STD_LOGIC;
   SIGNAL clk                   : STD_LOGIC := '1';
   SIGNAL rst                   : STD_LOGIC := '1';
+  SIGNAL sl1                   : STD_LOGIC := '1';
 
   SIGNAL node_index            : NATURAL := 0;
 
   SIGNAL stream_en_arr         : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');  -- default all streams are enabled
 
   SIGNAL ref_siso_arr          : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-  SIGNAL ref_sosi_arr          : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-  SIGNAL in_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL ref_sosi_arr          : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);                               -- generated stimuli
+  SIGNAL rx_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);  -- received stimuli
+  SIGNAL in_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);  -- input stimuli
 
   SIGNAL in_sync_arr           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
   SIGNAL in_sop_arr            : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
@@ -189,12 +200,9 @@ BEGIN
       -- Begin of stimuli
       FOR S IN 0 TO g_tb_nof_restart-1 LOOP
         v_bsn := c_bsn_init;
-        IF S = 2 THEN
-          stream_en_arr(1) <= '0';
-        END IF;
         FOR R IN 0 TO g_tb_nof_blocks-1 LOOP
           v_sync := sel_a_b(v_bsn MOD c_sync_period = c_sync_offset, '1', '0');
-          proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), clk, stream_en_arr(I), ref_siso_arr(I), ref_sosi_arr(I));
+          proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), clk, sl1, ref_siso_arr(I), ref_sosi_arr(I));
           v_bsn  := v_bsn + 1;
           v_data := v_data + g_block_size;
           proc_common_wait_some_cycles(clk, c_gap_size);  -- create gap between frames
@@ -206,6 +214,10 @@ BEGIN
       -- End of stimuli, g_bsn_latency_max blocks remain in DUT buffer
       expected_out_bsn_arr(I) <= TO_UVEC(v_bsn-1 - c_align_latency_nof_blocks, c_bsn_w);
       expected_out_data_arr(I) <= TO_UVEC(v_data-1 - c_align_latency_nof_valid, c_data_w);
+      IF I > 0 AND I = g_disable_stream THEN
+        -- Expected stream disable replacement value
+        expected_out_data_arr(I) <= TO_UVEC(g_replacement_value, c_data_w);
+      END IF;
 
       proc_common_wait_some_cycles(clk, 100);
       verify_done_arr(I) <= '1';
@@ -217,6 +229,9 @@ BEGIN
     END PROCESS;
   END GENERATE;
 
+  -- Model remote input stream enable/disable
+  stream_en_arr(g_disable_stream) <= '0' WHEN g_disable_stream > 0;
+
   -- Use tb_state to view tb progress in Wave window
   restart_cnt <= restart_cnt_arr(0);
 
@@ -228,11 +243,13 @@ BEGIN
     IF restart_cnt > 1 THEN tb_state <= s_restart; END IF;
   END PROCESS;
 
-  -- Create latency misalignment between the input streams
-  gen_in_sosi_arr : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE
-    in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * clk_period;
+  -- Model misalignment latency between the input streams
+  gen_rx_sosi_arr : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE
+    rx_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * clk_period;
   END GENERATE;
 
+  -- Model lost input
+  in_sosi_arr <= rx_sosi_arr;
 
   tb_end <= vector_and(tb_end_arr);
   

libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd

@@ -52,6 +52,7 @@ BEGIN
   -- g_bsn_w                      : NATURAL := c_dp_stream_bsn_w;  -- number of bits in sosi BSN
   -- g_data_w                     : NATURAL := 16;     -- number of bits in sosi data
   -- c_replacement_value          : INTEGER := 0;      -- output sosi data replacement value for missing input blocks
+  -- g_disable_stream             : NATURAL := 0;      -- default 0 to enable all streams, > 0 selects stream that will be disabled
   -- g_use_mm_output              : BOOLEAN := FALSE;  -- output via MM or via streaming DP
   -- g_pipeline_input             : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure
   -- g_rd_latency                 : NATURAL := 2;      -- 1 or 2, choose 2 to ease timing closure
@@ -61,10 +62,11 @@ BEGIN
   -- g_tb_nof_restart       : NATURAL := 1;       -- number of times to restart the input stimuli
   -- g_tb_nof_blocks        : NATURAL := 10       -- number of input blocks per restart
 
-  u_mm_output          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17,  TRUE, 0, 1,                0, 1, 50);
-  u_dp_output          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1,                0, 1, 50);
+  u_mm_output          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, 0,  TRUE, 0, 1,                0, 1, 50);
+  u_dp_output          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, 0, FALSE, 0, 1,                0, 1, 50);
+  u_dp_disable         : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (4, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, 2, FALSE, 0, 1,                0, 1, 50);
 
-  u_diff_delay_no_loss : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1,      c_delay_max, 1, 50);
-  --u_loss_replacement   : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1, 40 + c_delay_max, 1, 50);
+  u_diff_delay_no_loss : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, 0, FALSE, 0, 1,      c_delay_max, 1, 50);
+  --u_loss_replacement   : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, 0, FALSE, 0, 1, 40 + c_delay_max, 1, 50);
 
 END tb;