From 3902d2dd9341eec12bd3f4512bc3566fc03275db Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Tue, 5 Oct 2021 17:00:50 +0200
Subject: [PATCH] Use v.busy, instead of r.busy, to allow start_pulse at
mm_done, to support zero gaps between output blocks.
---
libraries/base/dp/src/vhdl/dp_block_from_mm.vhd | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 37b58b49b7..795c772f56 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -124,7 +124,11 @@ BEGIN
IF r.busy = '0' AND start_pulse = '1' THEN
-- initiate next block
v.busy := '1';
- ELSIF r.busy = '1' THEN
+ END IF;
+
+ -- use v.busy, instead of r.busy, to allow start_pulse at mm_done, to
+ -- support zero gaps between output blocks
+ IF v.busy = '1' THEN
IF out_siso.ready = '1' THEN
-- continue with block
mm_mosi.rd <= '1';
--
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