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Commit 30568303 authored by Eric Kooistra's avatar Eric Kooistra
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hdl_lib_technology = ip_arria10_e3sge3

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with 115 additions and 10 deletions
...@@ -117,6 +117,7 @@ if ctrl_wg.agwn_sigma>0 ...@@ -117,6 +117,7 @@ if ctrl_wg.agwn_sigma>0
end end
%ctrl_wg.ampl = 0.01; %ctrl_wg.ampl = 0.01;
ctrl_wg.freq = tb.subband_wg/tb.subband_fft_size; % normalized fs ctrl_wg.freq = tb.subband_wg/tb.subband_fft_size; % normalized fs
ctrl_wg.df = 0; % increment freq by df per block to create chirp
ctrl_wg.phase = 0; % normalized 2pi ctrl_wg.phase = 0; % normalized 2pi
if ctrl_wg.freq == 0 if ctrl_wg.freq == 0
ctrl_wg.offset = 1; % DC offset ctrl_wg.offset = 1; % DC offset
......
...@@ -2,6 +2,11 @@ hdl_lib_name = detector ...@@ -2,6 +2,11 @@ hdl_lib_name = detector
hdl_library_clause_name = detector_lib hdl_library_clause_name = detector_lib
hdl_lib_uses_synth = common technology mm ip_arria10_fifo ip_stratixiv_fifo tech_fifo dp ip_stratixiv_ram ip_arria10_ram tech_memory hdl_lib_uses_synth = common technology mm ip_arria10_fifo ip_stratixiv_fifo tech_fifo dp ip_stratixiv_ram ip_arria10_ram tech_memory
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_fifo ip_stratixiv_fifo_lib
ip_arria10_fifo ip_arria10_fifo_lib
ip_stratixiv_ram ip_stratixiv_ram_lib
ip_arria10_ram ip_arria10_ram_lib
synth_files = synth_files =
$RADIOHDL/applications/rfidb/designs/rfidb/src/vhdl/alt_probe.vhd $RADIOHDL/applications/rfidb/designs/rfidb/src/vhdl/alt_probe.vhd
......
...@@ -2,7 +2,7 @@ hdl_lib_name = unb2a_test_10GbE ...@@ -2,7 +2,7 @@ hdl_lib_name = unb2a_test_10GbE
hdl_library_clause_name = unb2a_test_10GbE_lib hdl_library_clause_name = unb2a_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology = ip_arria10_e3sge3
hdl_lib_include_ip = hdl_lib_include_ip =
# Comment all IP that is not used in this design # Comment all IP that is not used in this design
# 10GbE # 10GbE
......
...@@ -12,9 +12,31 @@ hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_ ...@@ -12,9 +12,31 @@ hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_
ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12
ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24
ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_phy_10gbase_r ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
ip_arria10_phy_10gbase_r_4 ip_arria10_phy_10gbase_r_4_altera_xcvr_native_a10_150
ip_arria10_phy_10gbase_r_12 ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
ip_arria10_phy_10gbase_r_24 ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
ip_arria10_phy_10gbase_r_48 ip_arria10_phy_10gbase_r_48_altera_xcvr_native_a10_150
ip_arria10_transceiver_pll_10g ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_150
ip_arria10_transceiver_reset_controller_1 ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_150
ip_arria10_transceiver_reset_controller_4 ip_arria10_transceiver_reset_controller_4_altera_xcvr_reset_control_150
ip_arria10_transceiver_reset_controller_12 ip_arria10_transceiver_reset_controller_12_altera_xcvr_reset_control_150
ip_arria10_transceiver_reset_controller_24 ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
ip_arria10_transceiver_reset_controller_48 ip_arria10_transceiver_reset_controller_48_altera_xcvr_reset_control_150
ip_arria10_e3sge3_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r_altera_xcvr_native_a10_151
ip_arria10_e3sge3_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4_altera_xcvr_native_a10_151
ip_arria10_e3sge3_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12_altera_xcvr_native_a10_151
ip_arria10_e3sge3_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24_altera_xcvr_native_a10_151
ip_arria10_e3sge3_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48_altera_xcvr_native_a10_151
ip_arria10_e3sge3_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
ip_arria10_e3sge3_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
synth_files = synth_files =
sim_10gbase_r.vhd sim_10gbase_r.vhd
......
...@@ -4,6 +4,9 @@ hdl_lib_uses_synth = technology common ...@@ -4,6 +4,9 @@ hdl_lib_uses_synth = technology common
hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
synth_files = synth_files =
tech_clkbuf_component_pkg.vhd tech_clkbuf_component_pkg.vhd
......
...@@ -16,6 +16,21 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master ...@@ -16,6 +16,21 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_master_lib
ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_slave_lib
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_lib
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_lib
ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_16g_dual_rank_800_lib
ip_arria10_ddr4_4g_1600 ip_arria10_ddr4_4g_1600_altera_emif_150
ip_arria10_ddr4_4g_2000 ip_arria10_ddr4_4g_2000_altera_emif_150
ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_8g_2400_altera_emif_150
ip_arria10_e3sge3_ddr4_4g_1600 ip_arria10_e3sge3_ddr4_4g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
synth_files = synth_files =
tech_ddr_pkg.vhd tech_ddr_pkg.vhd
......
...@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_fifo_lib ...@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_fifo_lib
hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_fifo ip_stratixiv_fifo_lib
ip_arria10_fifo ip_arria10_fifo_lib
ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib
synth_files = synth_files =
tech_fifo_component_pkg.vhd tech_fifo_component_pkg.vhd
......
hdl_lib_name = tech_flash hdl_lib_name = tech_flash
hdl_library_clause_name = tech_flash_lib hdl_library_clause_name = tech_flash_lib
hdl_lib_uses_synth = technology hdl_lib_uses_synth = technology
ip_stratixiv_flash
ip_arria10_asmi_parallel ip_arria10_asmi_parallel
ip_arria10_remote_update ip_arria10_remote_update
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_flash ip_stratixiv_flash_lib
ip_arria10_asmi_parallel ip_arria10_asmi_parallel_altera_asmi_parallel_150
ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
synth_files = synth_files =
tech_flash_component_pkg.vhd tech_flash_component_pkg.vhd
......
...@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_fpga_temp_sens_lib ...@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_fpga_temp_sens_lib
hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
synth_files = synth_files =
tech_fpga_temp_sens_component_pkg.vhd tech_fpga_temp_sens_component_pkg.vhd
......
...@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_fpga_voltage_sens_lib ...@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_fpga_voltage_sens_lib
hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
synth_files = synth_files =
tech_fpga_voltage_sens_component_pkg.vhd tech_fpga_voltage_sens_component_pkg.vhd
......
...@@ -5,6 +5,11 @@ hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_ ...@@ -5,6 +5,11 @@ hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_
ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150
ip_arria10_fractional_pll_clk125 ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
synth_files = synth_files =
tech_fractional_pll_component_pkg.vhd tech_fractional_pll_component_pkg.vhd
......
...@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_iobuf_lib ...@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_iobuf_lib
hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_ddio ip_stratixiv_ddio_lib
ip_arria10_ddio ip_arria10_ddio_lib
ip_arria10_e3sge3_ddio ip_arria10_e3sge3_ddio_lib
synth_files = synth_files =
tech_iobuf_component_pkg.vhd tech_iobuf_component_pkg.vhd
......
-- ip_stratixiv_phy_xaui_0.vhd -- ip_stratixiv_phy_xaui_0.vhd
-- Generated using ACDS version 11.1sp2 259 at 2016.03.29.08:44:51 -- Generated using ACDS version 11.1sp2 259 at 2016.05.17.15:40:35
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
......
-- ip_stratixiv_phy_xaui_soft.vhd -- ip_stratixiv_phy_xaui_soft.vhd
-- Generated using ACDS version 11.1sp2 259 at 2016.03.29.08:45:31 -- Generated using ACDS version 11.1sp2 259 at 2016.05.17.15:41:14
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
......
...@@ -4,6 +4,10 @@ hdl_lib_uses_synth = technology common dp ip_stratixiv_mac_10g ...@@ -4,6 +4,10 @@ hdl_lib_uses_synth = technology common dp ip_stratixiv_mac_10g
hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_mac_10g ip_stratixiv_mac_10g_lib
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
synth_files = synth_files =
tech_mac_10g_component_pkg.vhd tech_mac_10g_component_pkg.vhd
......
...@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_memory_lib ...@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_memory_lib
hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_ram ip_stratixiv_ram_lib
ip_arria10_ram ip_arria10_ram_lib
ip_arria10_e3sge3_ram ip_arria10_e3sge3_ram_lib
synth_files = synth_files =
tech_memory_component_pkg.vhd tech_memory_component_pkg.vhd
......
hdl_lib_name = tech_mult hdl_lib_name = tech_mult
hdl_library_clause_name = tech_mult_lib hdl_library_clause_name = tech_mult_lib
hdl_lib_uses_synth = common hdl_lib_uses_synth = common technology
technology
ip_stratixiv_mult ip_stratixiv_mult
ip_arria10_mult ip_arria10_mult
ip_arria10_complex_mult ip_arria10_complex_mult
...@@ -9,6 +8,12 @@ hdl_lib_uses_synth = common ...@@ -9,6 +8,12 @@ hdl_lib_uses_synth = common
ip_arria10_e3sge3_mult_add4_rtl ip_arria10_e3sge3_mult_add4_rtl
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_mult ip_stratixiv_mult_lib;
ip_arria10_mult ip_arria10_mult_lib
ip_arria10_complex_mult ip_arria10_complex_mult_altmult_complex_150
ip_arria10_complex_mult_rtl ip_arria10_complex_mult_rtl_lib
ip_arria10_e3sge3_mult_add4_rtl ip_arria10_e3sge3_mult_add4_rtl_lib
synth_files = synth_files =
tech_mult_component_pkg.vhd tech_mult_component_pkg.vhd
......
...@@ -7,6 +7,17 @@ hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arri ...@@ -7,6 +7,17 @@ hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arri
ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_pll ip_stratixiv_pll_lib
ip_stratixiv_pll_clk25 ip_stratixiv_pll_clk25_lib
ip_arria10_pll_clk200 ip_arria10_pll_clk200_altera_iopll_150
ip_arria10_pll_clk25 ip_arria10_pll_clk25_altera_iopll_150
ip_arria10_pll_clk125 ip_arria10_pll_clk125_altera_iopll_150
ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150
ip_arria10_e3sge3_pll_clk200 ip_arria10_e3sge3_pll_clk200_altera_iopll_151
ip_arria10_e3sge3_pll_clk25 ip_arria10_e3sge3_pll_clk25_altera_iopll_151
ip_arria10_e3sge3_pll_clk125 ip_arria10_e3sge3_pll_clk125_altera_iopll_151
ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
synth_files = synth_files =
tech_pll_component_pkg.vhd tech_pll_component_pkg.vhd
......
...@@ -6,6 +6,13 @@ hdl_lib_uses_ip = ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx ...@@ -6,6 +6,13 @@ hdl_lib_uses_ip = ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_lvds_lib
ip_stratixiv_tse_sgmii_gx ip_stratixiv_tse_sgmii_gx_lib
ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_lvds_altera_eth_tse_150
ip_arria10_tse_sgmii_gx ip_arria10_tse_sgmii_gx_altera_eth_tse_150
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
synth_files = synth_files =
tech_tse_component_pkg.vhd tech_tse_component_pkg.vhd
......
...@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_xaui_lib ...@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_xaui_lib
hdl_lib_uses_synth = technology ip_stratixiv_transceiver ip_stratixiv_phy_xaui tech_transceiver common dp hdl_lib_uses_synth = technology ip_stratixiv_transceiver ip_stratixiv_phy_xaui tech_transceiver common dp
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_transceiver ip_stratixiv_transceiver_lib
ip_stratixiv_phy_xaui ip_stratixiv_phy_xaui_lib
synth_files = synth_files =
sim_xaui.vhd sim_xaui.vhd
......
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