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Eric Kooistra authored
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hdllib.cfg 2.55 KiB
hdl_lib_name = tech_ddr
hdl_library_clause_name = tech_ddr_lib
hdl_lib_uses_synth = common
hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
ip_stratixiv_ddr3_uphy_16g_dual_rank_800
ip_arria10_ddr4_4g_1600
ip_arria10_ddr4_4g_2000
ip_arria10_ddr4_8g_2400
ip_arria10_e3sge3_ddr4_4g_1600
ip_arria10_e3sge3_ddr4_8g_1600
ip_arria10_e3sge3_ddr4_4g_2000
ip_arria10_e3sge3_ddr4_8g_2400
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_master_lib
ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_slave_lib
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_lib
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_lib
ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_16g_dual_rank_800_lib
ip_arria10_ddr4_4g_1600 ip_arria10_ddr4_4g_1600_altera_emif_150
ip_arria10_ddr4_4g_2000 ip_arria10_ddr4_4g_2000_altera_emif_150
ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_8g_2400_altera_emif_150
ip_arria10_e3sge3_ddr4_4g_1600 ip_arria10_e3sge3_ddr4_4g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
synth_files =
tech_ddr_pkg.vhd
sim_ddr.vhd
tech_ddr_component_pkg.vhd
tech_ddr_stratixiv.vhd
tech_ddr_arria10.vhd
tech_ddr_arria10_e3sge3.vhd
tech_ddr.vhd
test_bench_files =
tech_ddr_mem_model_component_pkg.vhd
tech_ddr_mem_model.vhd
regression_test_vhdl =
# no self checking tb available yet
[modelsim_project_file]
[quartus_project_file]