From 30568303197bb85502279b5aa703cb448ea44841 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 17 May 2016 14:18:29 +0000
Subject: [PATCH] hdl_lib_technology = ip_arria10_e3sge3
---
applications/apertif/matlab/two_pfb.m | 1 +
.../rfidb/librairies/detector/hdllib.cfg | 5 +
.../revisions/unb2a_test_10GbE/hdllib.cfg | 2 +-
libraries/technology/10gbase_r/hdllib.cfg | 24 +++-
libraries/technology/clkbuf/hdllib.cfg | 3 +
libraries/technology/ddr/hdllib.cfg | 17 ++-
libraries/technology/fifo/hdllib.cfg | 4 +
libraries/technology/flash/hdllib.cfg | 10 +-
.../technology/fpga_temp_sens/hdllib.cfg | 3 +
.../technology/fpga_voltage_sens/hdllib.cfg | 3 +
.../technology/fractional_pll/hdllib.cfg | 7 +-
libraries/technology/iobuf/hdllib.cfg | 4 +
.../ip_stratixiv_phy_xaui_0.vhd | 2 +-
.../ip_stratixiv_phy_xaui_soft.vhd | 2 +-
libraries/technology/mac_10g/hdllib.cfg | 4 +
libraries/technology/memory/hdllib.cfg | 4 +
libraries/technology/mult/hdllib.cfg | 9 +-
libraries/technology/pll/hdllib.cfg | 11 ++
libraries/technology/tse/hdllib.cfg | 7 ++
libraries/technology/xaui/hdllib.cfg | 3 +
tools/oneclick/base/hdl_config.py | 113 +++++++++++-------
tools/oneclick/base/modelsim_config.py | 28 +++--
.../base/modelsim_regression_test_vhdl.py | 2 +
tools/oneclick/base/quartus_config.py | 7 --
tools/oneclick/doc/hdltool_readme.txt | 51 +++++---
tools/oneclick/doc/readme_libraries.txt | 3 +
26 files changed, 242 insertions(+), 87 deletions(-)
diff --git a/applications/apertif/matlab/two_pfb.m b/applications/apertif/matlab/two_pfb.m
index 68e2bdaba0..fef84a0a63 100644
--- a/applications/apertif/matlab/two_pfb.m
+++ b/applications/apertif/matlab/two_pfb.m
@@ -117,6 +117,7 @@ if ctrl_wg.agwn_sigma>0
end
%ctrl_wg.ampl = 0.01;
ctrl_wg.freq = tb.subband_wg/tb.subband_fft_size; % normalized fs
+ctrl_wg.df = 0; % increment freq by df per block to create chirp
ctrl_wg.phase = 0; % normalized 2pi
if ctrl_wg.freq == 0
ctrl_wg.offset = 1; % DC offset
diff --git a/applications/rfidb/librairies/detector/hdllib.cfg b/applications/rfidb/librairies/detector/hdllib.cfg
index 063eedd992..035582141b 100644
--- a/applications/rfidb/librairies/detector/hdllib.cfg
+++ b/applications/rfidb/librairies/detector/hdllib.cfg
@@ -2,6 +2,11 @@ hdl_lib_name = detector
hdl_library_clause_name = detector_lib
hdl_lib_uses_synth = common technology mm ip_arria10_fifo ip_stratixiv_fifo tech_fifo dp ip_stratixiv_ram ip_arria10_ram tech_memory
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_fifo ip_stratixiv_fifo_lib
+ ip_arria10_fifo ip_arria10_fifo_lib
+ ip_stratixiv_ram ip_stratixiv_ram_lib
+ ip_arria10_ram ip_arria10_ram_lib
synth_files =
$RADIOHDL/applications/rfidb/designs/rfidb/src/vhdl/alt_probe.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 160828ab42..50560331d2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = unb2a_test_10GbE
hdl_library_clause_name = unb2a_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
-hdl_lib_technology =
+hdl_lib_technology = ip_arria10_e3sge3
hdl_lib_include_ip =
# Comment all IP that is not used in this design
# 10GbE
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index cec76fbbab..1b351c5222 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -12,9 +12,31 @@ hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_
ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12
ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24
ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48
-
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_arria10_phy_10gbase_r ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
+ ip_arria10_phy_10gbase_r_4 ip_arria10_phy_10gbase_r_4_altera_xcvr_native_a10_150
+ ip_arria10_phy_10gbase_r_12 ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
+ ip_arria10_phy_10gbase_r_24 ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
+ ip_arria10_phy_10gbase_r_48 ip_arria10_phy_10gbase_r_48_altera_xcvr_native_a10_150
+ ip_arria10_transceiver_pll_10g ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_150
+ ip_arria10_transceiver_reset_controller_1 ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_150
+ ip_arria10_transceiver_reset_controller_4 ip_arria10_transceiver_reset_controller_4_altera_xcvr_reset_control_150
+ ip_arria10_transceiver_reset_controller_12 ip_arria10_transceiver_reset_controller_12_altera_xcvr_reset_control_150
+ ip_arria10_transceiver_reset_controller_24 ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
+ ip_arria10_transceiver_reset_controller_48 ip_arria10_transceiver_reset_controller_48_altera_xcvr_reset_control_150
+ ip_arria10_e3sge3_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r_altera_xcvr_native_a10_151
+ ip_arria10_e3sge3_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4_altera_xcvr_native_a10_151
+ ip_arria10_e3sge3_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12_altera_xcvr_native_a10_151
+ ip_arria10_e3sge3_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24_altera_xcvr_native_a10_151
+ ip_arria10_e3sge3_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48_altera_xcvr_native_a10_151
+ ip_arria10_e3sge3_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+ ip_arria10_e3sge3_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1_altera_xcvr_reset_control_151
+ ip_arria10_e3sge3_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4_altera_xcvr_reset_control_151
+ ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151
+ ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
+ ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
synth_files =
sim_10gbase_r.vhd
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index b442fb41b7..65ae3c75e1 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -4,6 +4,9 @@ hdl_lib_uses_synth = technology common
hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
+ ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index c574756270..b05e8e080a 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -16,7 +16,22 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141
hdl_lib_technology =
-
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_master_lib
+ ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_slave_lib
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_lib
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_lib
+ ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_16g_dual_rank_800_lib
+ ip_arria10_ddr4_4g_1600 ip_arria10_ddr4_4g_1600_altera_emif_150
+ ip_arria10_ddr4_4g_2000 ip_arria10_ddr4_4g_2000_altera_emif_150
+ ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_8g_2400_altera_emif_150
+ ip_arria10_e3sge3_ddr4_4g_1600 ip_arria10_e3sge3_ddr4_4g_1600_altera_emif_151
+ ip_arria10_e3sge3_ddr4_8g_1600 ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
+ ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
+ ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
+ ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
+ ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
+
synth_files =
tech_ddr_pkg.vhd
sim_ddr.vhd
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index 3171d4a814..d9be8a27aa 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_fifo_lib
hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_fifo ip_stratixiv_fifo_lib
+ ip_arria10_fifo ip_arria10_fifo_lib
+ ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib
synth_files =
tech_fifo_component_pkg.vhd
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 32a88c6b82..ded07cad52 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -1,14 +1,20 @@
hdl_lib_name = tech_flash
hdl_library_clause_name = tech_flash_lib
hdl_lib_uses_synth = technology
- ip_stratixiv_flash
+
ip_arria10_asmi_parallel
ip_arria10_remote_update
ip_arria10_e3sge3_asmi_parallel
ip_arria10_e3sge3_remote_update
hdl_lib_uses_sim =
hdl_lib_technology =
-
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_flash ip_stratixiv_flash_lib
+ ip_arria10_asmi_parallel ip_arria10_asmi_parallel_altera_asmi_parallel_150
+ ip_arria10_remote_update ip_arria10_remote_update_altera_remote_update_150
+ ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
+ ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
+
synth_files =
tech_flash_component_pkg.vhd
tech_flash_asmi_parallel.vhd
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index defce62065..f7a6d5baf1 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_fpga_temp_sens_lib
hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
+ ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 0cdb78df86..15065eb71f 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_fpga_voltage_sens_lib
hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
+ ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index 25a6c9dddf..3a19fc5d6d 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -5,7 +5,12 @@ hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_
ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125
hdl_lib_uses_sim =
hdl_lib_technology =
-
+hdl_lib_disclose_library_clause_names =
+ ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150
+ ip_arria10_fractional_pll_clk125 ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
+ ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
+ ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
+
synth_files =
tech_fractional_pll_component_pkg.vhd
tech_fractional_pll_clk200.vhd
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index e5881d26e0..382e5f2766 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_iobuf_lib
hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_ddio ip_stratixiv_ddio_lib
+ ip_arria10_ddio ip_arria10_ddio_lib
+ ip_arria10_e3sge3_ddio ip_arria10_e3sge3_ddio_lib
synth_files =
tech_iobuf_component_pkg.vhd
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
index 9655c20d44..f0bda1c332 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
@@ -1,6 +1,6 @@
-- ip_stratixiv_phy_xaui_0.vhd
--- Generated using ACDS version 11.1sp2 259 at 2016.03.29.08:44:51
+-- Generated using ACDS version 11.1sp2 259 at 2016.05.17.15:40:35
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
index 0a66ff3f1e..f9ee88a0be 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
@@ -1,6 +1,6 @@
-- ip_stratixiv_phy_xaui_soft.vhd
--- Generated using ACDS version 11.1sp2 259 at 2016.03.29.08:45:31
+-- Generated using ACDS version 11.1sp2 259 at 2016.05.17.15:41:14
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index 9f68232d9f..a2332f7b0a 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -4,6 +4,10 @@ hdl_lib_uses_synth = technology common dp ip_stratixiv_mac_10g
hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_mac_10g ip_stratixiv_mac_10g_lib
+ ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
+ ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
synth_files =
tech_mac_10g_component_pkg.vhd
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 9a30fa1d22..1415618394 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -3,6 +3,10 @@ hdl_library_clause_name = tech_memory_lib
hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_ram ip_stratixiv_ram_lib
+ ip_arria10_ram ip_arria10_ram_lib
+ ip_arria10_e3sge3_ram ip_arria10_e3sge3_ram_lib
synth_files =
tech_memory_component_pkg.vhd
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 5d02f6cbc8..b769aab731 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -1,7 +1,6 @@
hdl_lib_name = tech_mult
hdl_library_clause_name = tech_mult_lib
-hdl_lib_uses_synth = common
- technology
+hdl_lib_uses_synth = common technology
ip_stratixiv_mult
ip_arria10_mult
ip_arria10_complex_mult
@@ -9,6 +8,12 @@ hdl_lib_uses_synth = common
ip_arria10_e3sge3_mult_add4_rtl
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_mult ip_stratixiv_mult_lib;
+ ip_arria10_mult ip_arria10_mult_lib
+ ip_arria10_complex_mult ip_arria10_complex_mult_altmult_complex_150
+ ip_arria10_complex_mult_rtl ip_arria10_complex_mult_rtl_lib
+ ip_arria10_e3sge3_mult_add4_rtl ip_arria10_e3sge3_mult_add4_rtl_lib
synth_files =
tech_mult_component_pkg.vhd
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index 32cbf9cd2e..464015e19b 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -7,6 +7,17 @@ hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arri
ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_pll ip_stratixiv_pll_lib
+ ip_stratixiv_pll_clk25 ip_stratixiv_pll_clk25_lib
+ ip_arria10_pll_clk200 ip_arria10_pll_clk200_altera_iopll_150
+ ip_arria10_pll_clk25 ip_arria10_pll_clk25_altera_iopll_150
+ ip_arria10_pll_clk125 ip_arria10_pll_clk125_altera_iopll_150
+ ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150
+ ip_arria10_e3sge3_pll_clk200 ip_arria10_e3sge3_pll_clk200_altera_iopll_151
+ ip_arria10_e3sge3_pll_clk25 ip_arria10_e3sge3_pll_clk25_altera_iopll_151
+ ip_arria10_e3sge3_pll_clk125 ip_arria10_e3sge3_pll_clk125_altera_iopll_151
+ ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 5518d12b7b..a386155b81 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -6,6 +6,13 @@ hdl_lib_uses_ip = ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_lvds_lib
+ ip_stratixiv_tse_sgmii_gx ip_stratixiv_tse_sgmii_gx_lib
+ ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_lvds_altera_eth_tse_150
+ ip_arria10_tse_sgmii_gx ip_arria10_tse_sgmii_gx_altera_eth_tse_150
+ ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
+ ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
synth_files =
tech_tse_component_pkg.vhd
diff --git a/libraries/technology/xaui/hdllib.cfg b/libraries/technology/xaui/hdllib.cfg
index 405e7711af..cdb973c141 100644
--- a/libraries/technology/xaui/hdllib.cfg
+++ b/libraries/technology/xaui/hdllib.cfg
@@ -3,6 +3,9 @@ hdl_library_clause_name = tech_xaui_lib
hdl_lib_uses_synth = technology ip_stratixiv_transceiver ip_stratixiv_phy_xaui tech_transceiver common dp
hdl_lib_uses_sim =
hdl_lib_technology =
+hdl_lib_disclose_library_clause_names =
+ ip_stratixiv_transceiver ip_stratixiv_transceiver_lib
+ ip_stratixiv_phy_xaui ip_stratixiv_phy_xaui_lib
synth_files =
sim_xaui.vhd
diff --git a/tools/oneclick/base/hdl_config.py b/tools/oneclick/base/hdl_config.py
index fb3c3bffbd..4aeb5a8763 100644
--- a/tools/oneclick/base/hdl_config.py
+++ b/tools/oneclick/base/hdl_config.py
@@ -54,6 +54,7 @@ import os.path
import shutil
from distutils.dir_util import copy_tree
import argparse
+import collections
class HdlConfig:
@@ -78,18 +79,24 @@ class HdlConfig:
['ip_stratixiv', 'ip_arria10'] : The HDL libraries with a hdl_lib_technology that is not '' or does not match one of the technologies
in technologyNames are removed from the list of HDL library dictionaries.
- - self.removed_dicts = contains the HDL library dicts that have been removed from self.libs.dicts because they are for
+ - self.removed_dicts = contains the HDL library dicts that have been removed from self.libs.dicts, because they are for
a technology that is not within technologyNames.
- self.removed_lib_names = the library names of self.removed_dicts
- Keep lists of all unknown library names that were found at the hdl_lib_uses_synth, hdl_lib_uses_ip, hdl_lib_uses_sim and
+ Keep lists of all unavailable library names that were found at the hdl_lib_uses_synth, hdl_lib_uses_ip, hdl_lib_uses_sim and
hdl_lib_include_ip keys in the self.libs.dicts:
- - self.unknown_use_libs = self.unknown_use_synth_libs + self.unknown_use_ip_libs + self.unknown_use_sim_libs
- - self.unknown_include_ip_libs
+ - self.unavailable_use_libs = self.unavailable_use_synth_libs + self.unavailable_use_ip_libs + self.unavailable_use_sim_libs
+ - self.unavailable_include_ip_libs
+
+ Unavailable used libraries can be missing for a valid reason when they are not required (e.g. IP for another technology). Being able to
+ ignore missing libraries does require that the entities from these libraries are instantiated as components in the VHDL. The difference
+ between a removed library and an unavailable library is that for a removed library the HDL config information is still known, whereas
+ for an unavailable library it is not. Therefore the library clause names for referred but unavailable HDL libraries are disclosed at the
+ 'hdl_lib_disclose_library_clause_names' keys of the libraries that use them and kept in a dictionary:
+
+ - self.disclosed_library_clause_names
- Unknown used libraries can be missing for a valid reason when they are not required (e.g. IP for another technology). Being able to
- ignore missing libraries does require that the entities from these libraries are instantiated as components in the VHDL.
"""
self.toolRootDir = toolRootDir
@@ -131,13 +138,26 @@ class HdlConfig:
# Update list of HDL library names
self.lib_names = self.libs.get_key_values('hdl_lib_name')
+ # create dictionary of library names with library clause names that are disclosed at the 'hdl_lib_disclose_library_clause_names' keys.
+ self.disclosed_library_clause_names = collections.OrderedDict()
+ for lib_dict in self.libs.dicts:
+ if 'hdl_lib_disclose_library_clause_names' in lib_dict:
+ key_values = lib_dict['hdl_lib_disclose_library_clause_names'].split()
+ lib_name = key_values[0::2]
+ lib_clause_name = key_values[1::2]
+ lib_pairs = zip(lib_name, lib_clause_name)
+ # No need to check for duplicate lib_names, because a dictionary cannot have duplicate keys
+ for lp in lib_pairs:
+ self.disclosed_library_clause_names[lp[0]] = lp[1]
+
# Check whether the used libraries from the self.libs.dicts keys indeed exist, otherwise remove them from the dictionary key
- # string and add the used library name to the list of unknown used library names. In this way other methods do not have to
- # check a used library does indeed exist.
- self.unknown_use_synth_libs = []
- self.unknown_use_ip_libs = []
- self.unknown_use_sim_libs = []
- self.unknown_include_ip_libs = []
+ # string and add the used library name to the list of unavailable used library names and check that the library use clause
+ # name was disclosed at the 'hdl_lib_disclose_library_clause_names' key. In this way other methods do not have to check a
+ # used library does indeed exist.
+ self.unavailable_use_synth_libs = []
+ self.unavailable_use_ip_libs = []
+ self.unavailable_use_sim_libs = []
+ self.unavailable_include_ip_libs = []
for lib_dict in self.libs.dicts:
lib_name = lib_dict['hdl_lib_name']
use_synth_libs = []
@@ -155,26 +175,34 @@ class HdlConfig:
for use_name in use_synth_libs:
if (use_name not in self.lib_names) and (use_name not in self.removed_lib_names):
lib_dict['hdl_lib_uses_synth']=cm.remove_from_list_string(lib_dict['hdl_lib_uses_synth'], use_name)
- self.unknown_use_synth_libs.append(use_name)
+ self.unavailable_use_synth_libs.append(use_name)
+ if use_name not in self.disclosed_library_clause_names.keys():
+ sys.exit("Error : Unavailable library %s at 'hdl_lib_uses_synth' key is not disclosed at 'hdl_lib_disclose_library_clause_names' key in library %s" % (use_name, lib_name))
for use_name in use_ip_libs:
if (use_name not in self.lib_names) and (use_name not in self.removed_lib_names):
lib_dict['hdl_lib_uses_ip']=cm.remove_from_list_string(lib_dict['hdl_lib_uses_ip'], use_name)
- self.unknown_use_ip_libs.append(use_name)
+ self.unavailable_use_ip_libs.append(use_name)
+ if use_name not in self.disclosed_library_clause_names.keys():
+ sys.exit("Error : Unavailable library %s at 'hdl_lib_uses_ip' key is not disclosed at 'hdl_lib_disclose_library_clause_names' key in library %s" % (use_name, lib_name))
for use_name in use_sim_libs:
if (use_name not in self.lib_names) and (use_name not in self.removed_lib_names):
lib_dict['hdl_lib_uses_sim']=cm.remove_from_list_string(lib_dict['hdl_lib_uses_sim'], use_name)
- self.unknown_use_sim_libs.append(use_name)
+ self.unavailable_use_sim_libs.append(use_name)
+ if use_name not in self.disclosed_library_clause_names.keys():
+ sys.exit("Error : Unavailable library %s at 'hdl_lib_uses_sim' key is not disclosed at 'hdl_lib_disclose_library_clause_names' key in library %s" % (use_name, lib_name))
for use_name in include_ip_libs:
if (use_name not in self.lib_names) and (use_name not in self.removed_lib_names):
lib_dict['hdl_lib_include_ip']=cm.remove_from_list_string(lib_dict['hdl_lib_include_ip'], use_name)
- self.unknown_include_ip_libs.append(use_name)
+ self.unavailable_include_ip_libs.append(use_name)
+ if use_name not in self.disclosed_library_clause_names.keys():
+ sys.exit("Error : Unavailable library %s at 'hdl_lib_include_ip' key in library %s is not disclosed at any 'hdl_lib_disclose_library_clause_names' key" % (use_name, lib_name))
# remove all duplicates from the list
- self.unknown_use_synth_libs = cm.unique(self.unknown_use_synth_libs)
- self.unknown_use_ip_libs = cm.unique(self.unknown_use_ip_libs)
- self.unknown_use_sim_libs = cm.unique(self.unknown_use_sim_libs)
- self.unknown_use_libs = self.unknown_use_synth_libs + self.unknown_use_ip_libs + self.unknown_use_sim_libs
- self.unknown_use_libs = cm.unique(self.unknown_use_libs) # aggregate list of use_*_libs
- self.unknown_include_ip_libs = cm.unique(self.unknown_include_ip_libs) # list of include_ip_use_libs
+ self.unavailable_use_synth_libs = cm.unique(self.unavailable_use_synth_libs)
+ self.unavailable_use_ip_libs = cm.unique(self.unavailable_use_ip_libs)
+ self.unavailable_use_sim_libs = cm.unique(self.unavailable_use_sim_libs)
+ self.unavailable_use_libs = self.unavailable_use_synth_libs + self.unavailable_use_ip_libs + self.unavailable_use_sim_libs
+ self.unavailable_use_libs = cm.unique(self.unavailable_use_libs) # aggregate list of use_*_libs
+ self.unavailable_include_ip_libs = cm.unique(self.unavailable_include_ip_libs) # list of include_ip_use_libs
def check_library_names(self, check_lib_names, lib_names=None):
@@ -185,7 +213,7 @@ class HdlConfig:
if lib_names==None: lib_names=self.lib_names
for check_lib_name in cm.listify(check_lib_names):
if check_lib_name not in cm.listify(lib_names):
- sys.exit('Error : Unknown HDL library name %s found with check_lib_name()' % check_lib_name)
+ sys.exit('Error : Unknown HDL library name %s found with %s' % (check_lib_name, cm.method_name()))
def get_used_libs(self, build_type, lib_dict, arg_include_ip_libs=[]):
@@ -280,7 +308,7 @@ class HdlConfig:
# remove all duplicates from the list
return cm.unique(all_use_libs)
else:
- sys.exit('Error : Unknown HDL library name %s in derive_all_use_libs()' % lib_name)
+ sys.exit('Error : Unknown HDL library name %s in %s()' % (lib_name, cm.method_name()))
def derive_lib_order(self, build_type, lib_name, lib_names=None):
@@ -411,6 +439,7 @@ class HdlConfig:
tech_dict = self.tool.read_dict_file(fileNamePath)
return tech_dict
+
def copy_files(self, build_type, lib_names=None):
"""Copy all source directories and source files listed at the <tool_name>_copy_files key. The build_type selects the <tool_name>_copy_files key using the
tool_name_<build_type> key value from the hdltool_<toolset>.cfg.
@@ -512,17 +541,27 @@ if __name__ == '__main__':
print 'Library paths :'
for p in hdl.libs.filePaths:
print ' ', p
-
+
print ''
print 'Library paths names :"'
for p in hdl.libs.filePathNames:
print ' ', p
-
+
print ''
print 'Library section headers :'
for lib_name in hdl.lib_names:
lib_dict = hdl.libs.dicts[hdl.lib_names.index(lib_name)]
print ' %-52s :' % lib_name, lib_dict['section_headers']
+
+ print ''
+ print 'get_lib_build_dirs for simulation:'
+ for build_dir in hdl.get_lib_build_dirs('sim'):
+ print ' ', build_dir
+
+ print ''
+ print 'get_lib_build_dirs for synthesis:'
+ for build_dir in hdl.get_lib_build_dirs('synth'):
+ print ' ', build_dir
print ''
print 'Removed library names = \n', hdl.removed_lib_names
@@ -531,23 +570,17 @@ if __name__ == '__main__':
print 'Library names = \n', hdl.lib_names
print ''
- print "Unknown library names in any 'hdl_lib_uses_synth' key = \n", hdl.unknown_use_synth_libs
- print "Unknown library names in any 'hdl_lib_uses_ip' key = \n", hdl.unknown_use_ip_libs
- print "Unknown library names in any 'hdl_lib_uses_sim' key = \n", hdl.unknown_use_sim_libs
- print ''
- print "Unknown library names in any 'hdl_lib_uses_*' key = \n", hdl.unknown_use_libs
- print ''
- print "Unknown library names in any 'hdl_lib_include_ip' key = \n", hdl.unknown_include_ip_libs
-
+ print "Unavailable library names in any 'hdl_lib_uses_synth' key = \n", hdl.unavailable_use_synth_libs
+ print "Unavailable library names in any 'hdl_lib_uses_ip' key = \n", hdl.unavailable_use_ip_libs
+ print "Unavailable library names in any 'hdl_lib_uses_sim' key = \n", hdl.unavailable_use_sim_libs
+ print "Unavailable library names in any 'hdl_lib_uses_*' key = \n", hdl.unavailable_use_libs
print ''
- print 'get_lib_build_dirs for simulation:'
- for build_dir in hdl.get_lib_build_dirs('sim'):
- print ' ', build_dir
+ print "Unavailable library names in any 'hdl_lib_include_ip' key = \n", hdl.unavailable_include_ip_libs
print ''
- print 'get_lib_build_dirs for synthesis:'
- for build_dir in hdl.get_lib_build_dirs('synth'):
- print ' ', build_dir
+ print "Used library clause names that are explicitly disclosed at the 'hdl_lib_disclose_library_clause_names' keys:"
+ for key in hdl.disclosed_library_clause_names.keys():
+ print ' %-52s : %s' % (key, hdl.disclosed_library_clause_names[key])
top_lib = 'dp'
top_lib = 'tech_xaui'
diff --git a/tools/oneclick/base/modelsim_config.py b/tools/oneclick/base/modelsim_config.py
index c821fd5357..2dfa92d8d3 100755
--- a/tools/oneclick/base/modelsim_config.py
+++ b/tools/oneclick/base/modelsim_config.py
@@ -176,11 +176,11 @@ class ModelsimConfig(hdl_config.HdlConfig):
Library mapping:
- Technology libraries that are available, but not used are mapped to work.
- - Unknown libraries are also mapped to work. The default library clause name is <lib_name> with postfix '_lib'. This is a best
- effort guess, because it is impossible to know the library clause name for an unknown library. If the best effort guess is
+ - Unavailable libraries are also mapped to work. The default library clause name is <lib_name> with postfix '_lib'. This is a best
+ effort guess, because it is impossible to know the library clause name for an unavailable library. If the best effort guess is
not suitable, then the workaround is to create a place holder directory with hdllib.cfg that defines the actual library clause
- name as it appears in the VHDL for the unknown HDL library. Unknown library names occur when e.g. a technology IP library is
- not available in the toolRootDir because it is not needed, or it may indicate a spelling error.
+ name as it appears in the VHDL for the unavailable HDL library. unavailable library names occur when e.g. a technology IP library
+ is not available in the toolRootDir because it is not needed, or it may indicate a spelling error.
"""
if lib_names==None: lib_names=self.lib_names
lib_dicts = self.libs.get_dicts('hdl_lib_name', lib_names)
@@ -202,10 +202,14 @@ class ModelsimConfig(hdl_config.HdlConfig):
# . not used vendor technology libs are not compiled but are mapped to work to avoid compile error when mentioned in the LIBRARY clause
for tech_dict in self.removed_dicts:
fp.write('%s = work\n' % tech_dict['hdl_library_clause_name'])
- # . unknown used libs are not compiled but are mapped to work to avoid compile error when mentioned in the LIBRARY clause
- for unknown_use_name in self.unknown_use_libs:
- # Assume the unknown library has a library clause name that has the default postfix '_lib'.
- fp.write('%s_lib = work\n' % unknown_use_name)
+ # . unavailable used libs are not compiled but are mapped to work to avoid compile error when mentioned in the LIBRARY clause
+ for unavailable_use_name in self.unavailable_use_libs:
+ # if the unavailable library is not in the dictionary of disclosed unavailable library clause names, then assume that the library clause
+ # name has the default postfix '_lib'.
+ if unavailable_use_name in self.disclosed_library_clause_names:
+ fp.write('%s = work\n' % self.disclosed_library_clause_names[unavailable_use_name])
+ else:
+ fp.write('%s_lib = work\n' % unavailable_use_name)
# . all used libs for this lib_name
use_lib_names = self.derive_all_use_libs('sim', lib_name)
use_lib_dicts = self.libs.get_dicts('hdl_lib_name', use_lib_names)
@@ -370,12 +374,12 @@ if __name__ == '__main__':
for sim_dir in msim.get_lib_build_dirs('sim'):
print ' ', sim_dir
- if len(msim.unknown_use_libs)>0 or len(msim.unknown_include_ip_libs)>0:
+ if len(msim.unavailable_use_libs)>0 or len(msim.unavailable_include_ip_libs)>0:
print ''
- print 'Note: Unknown library names occur when e.g. a technology IP library is not available in the toolRootDir because it is not needed,'
+ print 'Note: unavailable library names occur when e.g. a technology IP library is not available in the toolRootDir because it is not needed,'
print ' or it may indicate a spelling error.'
- print ". The following unknown library names were found at one or more 'hdl_lib_uses_*' key = ", msim.unknown_use_libs
- print ". The following unknown library names were found at one or more 'hdl_lib_include_ip' key = ", msim.unknown_include_ip_libs
+ print ". The following unavailable library names were found at one or more 'hdl_lib_uses_*' key = ", msim.unavailable_use_libs
+ print ". The following unavailable library names were found at one or more 'hdl_lib_include_ip' key = ", msim.unavailable_include_ip_libs
print ''
print 'Create library compile order files for simulation.'
diff --git a/tools/oneclick/base/modelsim_regression_test_vhdl.py b/tools/oneclick/base/modelsim_regression_test_vhdl.py
index ea78eb8e51..b8df77aa34 100644
--- a/tools/oneclick/base/modelsim_regression_test_vhdl.py
+++ b/tools/oneclick/base/modelsim_regression_test_vhdl.py
@@ -74,6 +74,8 @@ msim = modelsim_config.ModelsimConfig(toolRootDir=os.path.expandvars('$RADIOHDL/
# Get HDL library names for regression test
###############################################################################
lib_names = hdl_args.lib_names # Default use lib_names from command line
+msim.check_library_names('eric') # Check that the provided lib_names indeed exist
+braak
msim.check_library_names(lib_names) # Check that the provided lib_names indeed exist
if lib_names==[]:
lib_names=msim.lib_names # If no lib_names are provided then use all available HDL libraries
diff --git a/tools/oneclick/base/quartus_config.py b/tools/oneclick/base/quartus_config.py
index 8832486223..393e04de0f 100755
--- a/tools/oneclick/base/quartus_config.py
+++ b/tools/oneclick/base/quartus_config.py
@@ -254,13 +254,6 @@ if __name__ == '__main__':
else:
print ' %-40s' % d['hdl_lib_name'], ':', d['synth_top_level_entity']
- if len(qsyn.unknown_use_libs)>0 or len(qsyn.unknown_include_ip_libs)>0:
- print ''
- print 'Note: Unknown library names occur when e.g. a technology IP library is not available in the toolRootDir because it is not needed,'
- print ' or it may indicate a spelling error.'
- print ". The following unknown library names were found at one or more 'hdl_lib_uses_*' key = ", qsyn.unknown_use_libs
- print ". The following unknown library names were found at one or more 'hdl_lib_include_ip' key = ", qsyn.unknown_include_ip_libs
-
print ''
print 'Create Quartus IP library qip files for all HDL libraries in $%s.' % qsyn.libRootDir
qsyn.create_quartus_ip_lib_file()
diff --git a/tools/oneclick/doc/hdltool_readme.txt b/tools/oneclick/doc/hdltool_readme.txt
index df5fa446c4..95163fe48b 100644
--- a/tools/oneclick/doc/hdltool_readme.txt
+++ b/tools/oneclick/doc/hdltool_readme.txt
@@ -563,11 +563,18 @@ f) hdllib.cfg key descriptions
'The name of the HDL library as it is used in the VHDL LIBRARY clause, e.g. common_lib, dp_lib, unb1_minimal_lib.
- hdl_lib_uses_synth =
+ See also the other 'hdl_lib_include_*' descriptions.
List of HDL library names that are used in this HDL library for the 'synth_files', only the libraries that appear in
- VHDL LIBRARY clauses need to be mentioned, all lower level libraries are found automatically.
+ VHDL LIBRARY clauses need to be mentioned, all lower level libraries are found automatically. The following libraries
+ have to be declared at the 'hdl_lib_uses_synth' key:
+ - Libraries with packages that are used
+ - Library components that are instantiated as entities
+ Libraries that are instantiated as components can be specified at the 'hdl_lib_uses_synth' key, but instead it may also be
+ specified at the 'hdl_lib_uses_ip' key. If there are different source variants of the component and if these source lirbaries
+ can be missing in the 'lib_root_dir' tree, then the library must be specified at the 'hdl_lib_uses_ip' key.
- hdl_lib_uses_ip =
- See also 'hdl_lib_include_ip' description.
+ See also the other 'hdl_lib_include_*' descriptions.
The 'hdl_lib_uses_ip' typically defines IP libraries that have multiple variants even within a specific technology (as specified
by toolset key 'technology_names'). However typically only one tech variant of the IP is used in a design. The
'hdl_lib_include_ip' key therefore defines the library that must be included in the list of library dependencies that are derived
@@ -582,47 +589,55 @@ f) hdllib.cfg key descriptions
= ip_stratixiv_ddr3_uphy_4g_800_master in the hdllib.cfg of unb1_ddr3. Another example is ip_stratixiv_tse_sgmii_lvds for
tech_tse which is included by the board specific library unb1_board to avoid that the other ip_stratixiv_tse_sgmii_gx variant
is also include when it is not actually used. This example also shows that a 'hdl_lib_include_ip' can also occur at some
- intermediate hierarchical component level in a design. The advantage is that the include of ip_stratixiv_tse_sgmii_gx now
- automatically applies to all designs that instantiate unb1_board.
+ intermediate hierarchical component level in a design. The advantage is that the include of ip_stratixiv_tse_sgmii_lvds in
+ the unb1_board hdlib.cfg now automatically applies to all designs that instantiate unb1_board.
The exclusion can only be done when the component is instantiated as a component and not as a entity. Therefore the
exclusion is done at the IP level, because the IP is instantiated as component. Hence the exclusion works because for a
component instance that is not used, only the component declaration (in the component package) needs to be known by the
tools. Hence the exclusion makes use of the same VHDL component mechanism as the technology independence.
The exclusion is only done for synthesis, so not for simulation. The reason is that for simulation it is oke to keep the
- library included and also necessary to avoid a compile error when the library is mentioned in a LIBRARY clause. For
- IP libraries this occurs in the tech_*.vhd to declare IP libraries to ensure default binding in simulation, e.g. like in
- tech_ddr_stratixiv.vhd. This IP library clause is ignored by synthesis, so then the exclusion causes no errors.
+ library included.
The difference between this 'hdl_lib_uses_ip' key and the 'hdl_lib_technology' key is that the HDL libraries with
'hdl_lib_technology' key value that does not match the specified technologies are not build. Whereas HDL libraries that
are excluded via the combination of 'hdl_lib_include_ip' and 'hdl_lib_uses_ip' are still created in the build directory, but
they are not used for that HDL library so they are excluded dynamically.
- hdl_lib_uses_sim =
+ See also the other 'hdl_lib_include_*' descriptions.
List of HDL library names that are used in this HDL library for the 'test_bench_files', only the libraries that appear in
VHDL LIBRARY clauses need to be mentioned, all lower level libraries are found automatically.
- The hdl_lib_uses_synth key and hdl_lib_uses_sim key separate the dependencies due to the synth_files from the extra
- dependencies that come from the test bench files. Quartus can exit with error if IP is included in the hdl_lib_uses_synth
- list of libraries but not actually used in the design, eg due to a sdc file that is then sourced but that cannot find
- some IP signals. Having a seperate hdl_lib_uses_synth and hdl_lib_uses_sim key solves this issue, by avoiding that
- libraries that are only needed for test bench simulation get included in the list for synthesis. This seperation avoids
- that libraries that are only needed for the test bench simulations also get included in the list of libraries for
- synthesis. Often the 'test_bench_files' do not depend on other libraries, so then the 'hdl_lib_uses_sim' remains empty.
+ The 'hdl_lib_uses_synth' and 'hdl_lib_uses_ip' keys and 'hdl_lib_uses_sim' key separate the dependencies due to the synth_files
+ from the extra dependencies that come from the test bench files. Quartus can exit with error if IP is included in the
+ 'hdl_lib_uses_ip' list of libraries but not actually used in the design, eg due to a sdc file that is then sourced but
+ that cannot find some IP signals. Having a seperate 'hdl_lib_uses_ip' and 'hdl_lib_uses_sim' key solves this issue, by avoiding
+ that libraries that are only needed for test bench simulation get included in the list for synthesis. Often the
+ 'test_bench_files' do not depend on other libraries then those that are already mentioned at the 'hdl_lib_uses_synth' key, so
+ then the 'hdl_lib_uses_sim' remains empty.
- hdl_lib_include_ip =
- See also 'hdl_lib_uses_ip' description.
- The 'hdl_lib_uses_*' keys identify which libraries are available for that paricular HDL library. For simulation they are all
+ See also the 'hdl_lib_include_*' descriptions.
+ The 'hdl_lib_uses_*' keys identify which libraries are available for that particular HDL library. For simulation they are all
included. The 'hdl_lib_include_ip' identifies which IP libraries from 'hdl_lib_uses_ip' will actually be included for synthesis.
The 'hdl_lib_include_ip' typically appears in another higher layer HDL library. IP libraries can be includes in the following
ways:
. by listing the IP library name at the 'hdl_lib_uses_synth' key, then it is always included
. by listing the IP library name at the 'hdl_lib_uses_ip' key, and including it explicitly with the 'hdl_lib_include_ip' key.
The 'hdl_lib_include_ip' is typically set at:
- . the design library that actually uses that IP library, this then has to be done for every design
+ . the design library that actually uses that IP library, this then has to be done per design revision.
. for IP in unb*_board that is used in all designs it is set in these unb*_board libraries so that it is then automatically
included for all designs that use the unb*_board library (i.e. via ctrl_unb*_board.vhd).
- . Note that specifiying an IP library at the 'hdl_lib_uses_ip' key and then including it via 'hdl_lib_include_ip' in the same
+ . Note that specifying an IP library at the 'hdl_lib_uses_ip' key and then including it via 'hdl_lib_include_ip' in the same
hdllib.cfg, is equivalent to specifying the IP library at the 'hdl_lib_uses_synth' key.
+- hdl_lib_disclose_library_clause_names =
+ See also the 'hdl_lib_include_*' descriptions.
+ If a component from a library is instantiated as a component (instead of as an entity) then that means that this library may be
+ unavailable and then it has to be listed as a pair of lib_name and library_clause_name at this 'hdl_lib_disclose_library_clause_names'
+ key. For components that are instantiated as components the actual source library may have been removed (via the 'hdl_lib_technology'
+ key) or it may even not be present at all. The library clause name of instantiated components is used in the VHDL code at the LIBRARY
+ statement in e.g. a tech_*.vhd file to ensure default component binding in simulation. The 'hdl_lib_disclose_library_clause_names'
+ key is then used in the hdllib.cfg file of that (technology) wrapper library to disclose the library clause name of the component
+ library that is listed at the hdl_lib_uses_* key.
- hdl_lib_technology =
The IP technology that this library is using or targets, e.g. ip_stratixiv for UniBoard1, ip_arria10 for UniBoard2. For generic HDL libraries use ''.
diff --git a/tools/oneclick/doc/readme_libraries.txt b/tools/oneclick/doc/readme_libraries.txt
index 5bd345f2cd..0e5d953bf5 100644
--- a/tools/oneclick/doc/readme_libraries.txt
+++ b/tools/oneclick/doc/readme_libraries.txt
@@ -84,3 +84,6 @@ is IP dependent, but is not needed if that IP is not selected. In this way each
On top of the tech_<component_type> level there can be yet another functional level to ease the generic usage of the component in an application. This
extra level typically adds useful default functionality like eg. diagnostic test functionality and FIFOs in case of a PHY IO component. It may also
contain a simulation model for the PHY IO component.
+
+For IP libraries that are instantiated as components in the tech_*.vhd it is necessary to declare these IP libraries to ensure default binding in
+simulation, e.g. like in tech_ddr_stratixiv.vhd. This IP library clause is ignored by synthesis, so then the exclusion causes no errors.
--
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