Removed -arr fromddr3 port maps

applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd

@@ -24,6 +24,8 @@
 --          The DUT can be targeted at unb 0, bn3 with the same Python scripts 
 --          that are used on hardware. 
 
+LIBRARY ip_stratixiv_ddr3_mem_model_lib;
+
 LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, dp_lib, io_ddr_lib, eth_lib, technology_lib, tech_ddr_lib, diag_lib, reorder_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
@@ -88,15 +90,11 @@ ARCHITECTURE tb OF tb_unb1_reorder IS
   SIGNAL sens_scl            : STD_LOGIC;
   SIGNAL sens_sda            : STD_LOGIC;    
   
-    -- Signals to interface with the DDR3 memory model.
-  SIGNAL phy_in              : t_tech_ddr_phy_in_arr(0 DOWNTO 0);
-  SIGNAL phy_io              : t_tech_ddr_phy_io_arr(0 DOWNTO 0);
-  SIGNAL phy_ou              : t_tech_ddr_phy_ou_arr(0 DOWNTO 0);   
-  
-  SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
-  SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
-  SIGNAL we_n  : STD_LOGIC_VECTOR(0 DOWNTO 0);
-
+  -- Signals to interface with the DDR3 memory model.
+  SIGNAL phy_in              : t_tech_ddr3_phy_in;
+  SIGNAL phy_io              : t_tech_ddr3_phy_io;
+  SIGNAL phy_ou              : t_tech_ddr3_phy_ou;   
+   
   -- Model I2C sensor slaves as on the UniBoard
   CONSTANT c_fpga_temp_address   : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000";  -- MAX1618 address LOW LOW
   CONSTANT c_fpga_temp           : INTEGER := 60;
@@ -140,8 +138,8 @@ BEGIN
     GENERIC MAP (
       g_sim         => c_sim,
       g_sim_unb_nr  => c_unb_nr,
-      g_sim_node_nr => c_node_nr,
-      g_tech_ddr    => c_ddr
+      g_sim_node_nr => c_node_nr
+--      g_tech_ddr    => c_ddr
     )
     PORT MAP (
       -- GENERAL
@@ -175,12 +173,12 @@ BEGIN
   ------------------------------------------------------------------------------
   u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
   GENERIC MAP (
-    g_sim      => TRUE,
     g_tech_ddr => c_ddr
   )
   PORT MAP (
-    mem_in => phy_ou(0),
-    mem_io => phy_io(0)
+    mem3_in => phy_ou,
+    mem3_io => phy_io,
+    mem3_ou => phy_in
   );
   
   ------------------------------------------------------------------------------
@@ -221,52 +219,4 @@ BEGIN
     ana_volt_adin     => c_uniboard_adin
   ); 
   
---  -- DDR3 Model 
---  u_4gb_800_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
---	GENERIC MAP (
---		MEM_IF_CLK_EN_WIDTH          => 2,
---		MEM_IF_CK_WIDTH              => 2,
---		MEM_IF_BANKADDR_WIDTH        => 3,
---		MEM_IF_ADDR_WIDTH            => 15,
---		MEM_IF_ROW_ADDR_WIDTH        => 15,
---		MEM_IF_COL_ADDR_WIDTH        => 10,
---		MEM_IF_CS_WIDTH              => 2,
---		MEM_IF_CONTROL_WIDTH         => 1,
---		MEM_IF_ODT_WIDTH             => 2,
---		DEVICE_DEPTH                 => 1,
---		DEVICE_WIDTH                 => 1,
---		MEM_IF_CS_PER_RANK           => 1,
---		MEM_IF_DQS_WIDTH             => 8,
---		MEM_IF_DQ_WIDTH              => 64,
---		MEM_MIRROR_ADDRESSING_DEC    => 0,
---		MEM_TRTP                     => 3,
---		MEM_TRCD                     => 6,
---		MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
---		MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
---		MEM_REGDIMM_ENABLED          => 0,
---		MEM_INIT_EN                  => 0,
---		MEM_INIT_FILE                => "",
---		MEM_GUARANTEED_WRITE_INIT    => 0,
---		DAT_DATA_WIDTH               => 32,
---		MEM_VERBOSE                  => 1
---	)
---  PORT MAP (
---		mem_a       => phy_ou(0).a,
---		mem_ba      => phy_ou(0).ba,       
---		mem_ck      => phy_ou(0).ck,      
---		mem_ck_n    => phy_ou(0).ck_n,    
---		mem_cke     => phy_ou(0).cke,   
---		mem_cs_n    => phy_ou(0).cs_n,  
---		mem_dm      => phy_ou(0).dm,       
---		mem_ras_n   => phy_ou(0).ras_n,           
---		mem_cas_n   => phy_ou(0).cas_n,           
---		mem_we_n    => phy_ou(0).we_n,            
---		mem_reset_n => phy_ou(0).reset_n, 
---		mem_dq      => phy_io(0).dq,       
---		mem_dqs     => phy_io(0).dqs,      
---		mem_dqs_n   => phy_io(0).dqs_n,    
---		mem_odt     => phy_ou(0).odt       
---	);               
-  
-
 END tb;