-Removed arr from ddr3 port map

-moved bsn_mon to node

applications/unb1_reorder/src/vhdl/unb1_reorder.vhd

@@ -69,13 +69,9 @@ ENTITY unb1_reorder IS
     ETH_SGOUT     : OUT   STD_LOGIC;
     
     -- SO-DIMM Memory Bank I
---    MB_I_IN       : IN    t_tech_ddr_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);     
---    MB_I_IO       : INOUT t_tech_ddr_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0); 
---    MB_I_OU       : OUT   t_tech_ddr_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0) 
-
-    MB_I_IN       : IN    t_tech_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);     
-    MB_I_IO       : INOUT t_tech_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);     
-    MB_I_OU       : OUT   t_tech_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0)      
+    MB_I_IN       : IN    t_tech_ddr3_phy_in;     
+    MB_I_IO       : INOUT t_tech_ddr3_phy_io;     
+    MB_I_OU       : OUT   t_tech_ddr3_phy_ou      
   );
 END unb1_reorder;
 
@@ -85,7 +81,7 @@ ARCHITECTURE str OF unb1_reorder IS
   -- Constant definitions for ctrl_unb_common
   CONSTANT c_design_name      : STRING := "unb1_reorder";  
   CONSTANT c_design_note      : STRING := "Reference Reorder";
-  CONSTANT c_fw_version       : t_unb1_board_fw_version := (0, 10);  -- firmware version x.y
+  CONSTANT c_fw_version       : t_unb1_board_fw_version := (0, 11);  -- firmware version x.y
   CONSTANT c_use_phy          : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
   CONSTANT c_aux              : t_c_unb1_board_aux     := c_unb1_board_aux;
   CONSTANT c_app_led_en       : BOOLEAN                := TRUE;
@@ -221,8 +217,6 @@ ARCHITECTURE str OF unb1_reorder IS
   SIGNAL block_gen_src_out_arr      : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
   SIGNAL block_gen_src_in_arr       : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
 
-  SIGNAL bsn_sosi_arr               : t_dp_sosi_arr(1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-
   SIGNAL data_buf_snk_in_sosi_arr   : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
   SIGNAL data_buf_snk_out_siso_arr  : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
   
@@ -333,32 +327,6 @@ BEGIN
     ETH_SGOUT                => ETH_SGOUT
   ); 
   
-  u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
-  GENERIC MAP (
-    g_nof_streams        => 2, -- Check one input and one output stream
-    g_cross_clock_domain => TRUE,
-    g_bsn_w              => c_dp_stream_bsn_w,
-    g_cnt_sop_w          => c_word_w,
-    g_cnt_valid_w        => c_word_w,
-    g_log_first_bsn      => TRUE
-  )
-  PORT MAP (
-    -- Memory-mapped clock domain
-    mm_rst      => mm_rst,
-    mm_clk      => mm_clk,
-    reg_mosi    => reg_bsn_monitor_mosi,
-    reg_miso    => reg_bsn_monitor_miso,
-    
-    -- Streaming clock domain
-    dp_rst      => dp_rst,
-    dp_clk      => dp_clk,
-    in_siso_arr => (OTHERS=>c_dp_siso_rdy),
-    in_sosi_arr => bsn_sosi_arr
-  );
-  
-  bsn_sosi_arr(0) <= block_gen_src_out_arr(0);
-  bsn_sosi_arr(1) <= data_buf_snk_in_sosi_arr(0);
-  
   u_mmm : ENTITY work.mmm_unb1_reorder
   GENERIC MAP(
     g_sim         => g_sim,         
@@ -454,7 +422,7 @@ BEGIN
   GENERIC MAP(
     g_sim            => g_sim,       
     g_use_MB_I       => g_use_MB_I,  
---    g_tech_ddr       => g_tech_ddr,       
+    g_tech_ddr       => g_tech_ddr,       
     g_nof_streams    => c_nof_streams,   
     g_in_dat_w       => c_in_dat_w,      
     g_ena_pre_transp => c_ena_pre_transp,
@@ -489,6 +457,10 @@ BEGIN
     -- Reorder transpose      
     ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
     ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+    
+    -- BSN monitor
+    reg_bsn_monitor_mosi      => reg_bsn_monitor_mosi,
+    reg_bsn_monitor_miso      => reg_bsn_monitor_miso,
 
     -- SO-DIMM Memory Bank I = ddr3_I
     MB_I_in               =>  MB_I_IN,