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  • HPR-158
  • L2SDP-1082
  • L2SDP-LIFT
  • master default protected
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Created with Raphaël 2.2.029May28272622212015141312118764130Apr29282423222120171615141312109873231Mar3027262524232019181716131211109-Finished first generation of wrapper code.-Added experimental myHDL.-Added inc_comb.py + description in readme_myHDL.txt.-Added block generators.-Renamed signal.use the QSYS reset line for ethlet the board SDC file appear after the other IP related SDC filesusing QSYS reset line for eth, reconnect ID linescompiler options and SDC changesupdate for tool changesadded the fractional pll for clk125unbos compile option for UNB2 is: -DCOMPILE_FOR_GEN2_UNB2-Stripped down the VHDL files;-Cleaned up the SOPC.-Fixed paths.-Added hdllib.cfg.-Renamed file.-Added design apertif_unb1_fn_bf_emu.Added methods and classes Made a lot of changes. singlemac design and IP compiles with Q15.0pinning design compiles with Q15.0added the fractional PLL for clk125added the fractional pll IP for clk125mm_clk frequency back to 50MHz (as it was before)re-enabled PLLs, REMU and EPCSusing a CLKBUF in betweekn input clock and PLL.Added tech_clkbuf and tech-fractional_pllAdded g_use_clkbuf=TRUE to use ALTCLKCTRL. Added g_use_fpll=FALSE to use IOPLL, but the option is to use a fractional PLL.Added global clock buffer IPAdded fractional PLL IP with similar c0, c1 and c2 as the pll_clk200 IO PLL.Added fractional PLL IP with similar c0, c1 and c2 as the pll_clk200 IO PLL.Added global clock buffer IPthis (temporary) debug version has epcs,remu,plls removed and tse,mm_clkusing 125MHz clock for mm_clknew -t option documented for python scriptsCommented QSFP_* INOUT ports because they are not connected and thus cause a fitter warning.Debug: for single board application force bck_id = 0 to avoid need to set the bck_id input.-Undid use of environment var.