Added simple simulation model for voltage sensor.

libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd

@@ -108,12 +108,9 @@ BEGIN
 
   END GENERATE;
 
-  gen_no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE
-                                                                                
+  no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE                                                                              
     -- temp = (708 * adc)/1024 - 273 => adc = (temp + 273)*1024/708                                                             
-                                                             
     temp_data <= TO_UVEC(460, temp_data'LENGTH);   -- choose temp = 45 degrees so adc temp_data = 460
-    --temp_data <= RESIZE_UVEC(x"45",10);
     mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
   END GENERATE;
 
@@ -146,6 +143,10 @@ BEGIN
 
 
   -- voltage sensor
+  no_tech_fpga_voltage_sens: IF g_sim=TRUE GENERATE
+    -- Model the voltage sensor by returning the MM register address of the voltage field
+    reg_voltage_store_miso.rddata <= RESIZE_MEM_UDATA(reg_voltage_store_mosi.address(3 DOWNTO 0));
+  END GENERATE;
 
   gen_tech_fpga_voltage_sens: IF g_sim=FALSE GENERATE
     u_tech_fpga_voltage_sens : ENTITY tech_fpga_voltage_sens_lib.tech_fpga_voltage_sens