-Updated comment.

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -74,7 +74,8 @@
 --         its own (clk_a,clk_b) clock domain, which is not what we need here.
 --   . Downside of common_ram_r_w: it uses a single clock
 --     . This st_histogram.vhd operates in dp_clk domain only, so we need to 
---       provide MM access to the user, in the mm_clk domain, elsewhere.
+--       provide MM access to the user, in the mm_clk domain, elsewhere. This
+--       has been done in mms_st_histogram.vhd.
 
 LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;