-Updated comments.

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -24,6 +24,12 @@
 -- Purpose: 
 -- . Count incoming data values and keep the counts in RAM as a histogram
 -- Description: 
+--  . The contents of the inactive RAM is cleared automatically just before the
+--    next sync interval. This way, no data is lost and all valid input data
+--    contributes to the histogram. The ram_clearing status output is high
+--    during this automated clearing.
+--  . All valid data of a DC input contributes to the histogram, no data is 
+--    lost.
 --  . The block schematic below shows the data flow from snk_in to ram_mosi:
 --    . snk_in.data is interpreted as address (bin) to read from RAM by bin_reader.
 --      . a RAM pointer 0 or 1 is kept as MS part of the address.
@@ -55,6 +61,10 @@
 --   time these controls such that the active RAM page does not swap before these
 --   operation (ram_mosi readout) has finished.
 -- Remarks:
+-- . The RAM block we use basically needs 3 ports:
+--   1 - read port in dp_clk domain to read current bin value
+--   2 - write port in dp_clk domain to write back incremented bin value
+--   3 - read port in mm_clk domain to read the inactive page
 -- . common_ram_r_w
 --   . Why common_ram_r_w was selected: it uses a single clock
 --     . We need to read and write back bins in the dp_clk clock domain, so our RAM
@@ -362,14 +372,7 @@ BEGIN
 
 
   -------------------------------------------------------------------------------
-  -- ram_clear control input - let user clear the RAM
-  -- 1) User waits for PPS
-  -- 2) User reads data from RAM
-  --    . Logic here takes care that unused RAM is being read
-  -- 3) User sets ram_clear register
-  --    . Logic clears unused (at that exact time) RAM but does not compensate 
-  --      for user being late (the ram pointer is checked only the very moment 
-  --      ram_clear is set)
+  -- Clear the RAM just before the next sync interval
   -------------------------------------------------------------------------------
   -- Count input data for automatic RAM clear before next sync interval
   nxt_data_cnt <= (OTHERS=>'0') WHEN TO_UINT(data_cnt)=g_nof_data_per_sync-1 ELSE INCR_UVEC(data_cnt, 1) WHEN snk_in.valid='1' ELSE data_cnt;