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Commit 22e99c4b authored by Eric Kooistra's avatar Eric Kooistra
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Updated the yaml files for unb2b_minimal.

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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!71Resolve L2SDP-186
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boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
+ 39
− 32
View file @ 22e99c4b
......@@ -4,46 +4,53 @@ schema_type : fpga
hdl_library_name: unb2b_minimal
fpga_name : unb2b_minimal
fpga_description: "unb2b_minimal system"
fpga_description: "FPGA design unb2b_minimal"
peripherals:
- peripheral_name: unb2b_board/unb2b
slave_port_names:
- rom_system_info
- pio_system_info
- pio_wdi
- reg_wdi
- reg_unb_sens
- reg_unb_pmbus
- reg_fpga_temp_sens
- reg_fpga_voltage_sens
- ram_scrap
parameter_overrides:
- { name : g_sim, value: FALSE }
- { name : g_clk_freq, value: 125E6 }
- { name : g_temp_high, value: 85 }
- peripheral_name: unb2b_board/system_info
slave_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
lock_base_address: 0x0
lock_base_address: 0x4000
- peripheral_name: eth/eth1g
- peripheral_name: unb2b_board/wdi
slave_port_names:
- PIO_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
slave_port_names:
- avs_eth_0_tse
- avs_eth_0_reg
- avs_eth_0_ram
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
- peripheral_name: unb2b_board/ram_scrap
slave_port_names:
- RAM_SCRAP
- peripheral_name: eth/eth
slave_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
- peripheral_name: ppsh/ppsh
slave_port_names:
- pio_pps
- PIO_PPS
- peripheral_name: epcs/epcs
slave_port_names:
- reg_epcs
- reg_dpmm_ctrl
- reg_dpmm_data
- reg_mmdp_ctrl
- reg_mmdp_data
parameter_overrides:
- { name : g_sim_flash_model, value: FALSE }
- REG_EPCS
- peripheral_name: dp/dpmm
slave_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
- peripheral_name: dp/mmdp
slave_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
- peripheral_name: remu/remu
slave_port_names:
- reg_remu
\ No newline at end of file
- REG_REMU
boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+ 143
− 103
View file @ 22e99c4b
......@@ -3,122 +3,162 @@ schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name : unb2b_board
hdl_library_description: " This is the description for the unb2b_board package "
# <peripheral_group>_<peripheral_name>_<slave_name>_<slave_type>
hdl_library_name: unb2b_board # ctrl_unb2b_board.vhd
hdl_library_description: "Peripherals in unb2b_board."
peripherals:
- peripheral_name: unb2b
parameters:
- { name: g_sim, value: FALSE }
- { name: g_clk_freq, value: c_unb2b_board_mm_clk_freq_125M }
- { name: g_temp_high, value: 85 }
- peripheral_name: ram_scrap # pi_ram_scrap.py
peripheral_description: ""
slave_ports:
# rom_system_info
- slave_name : rom_system
slave_type : REG
# MM port for common_ram_r_w.vhd
- slave_name: RAM_SCRAP
slave_type: RAM
slave_description: "One memory mapped block RAM for MM access test purposes."
fields:
- - field_name : info
access_mode : RO
- - field_name: rw_data
field_description: "Void data"
access_mode: RW
address_offset: 0x0
number_of_fields: 8192
field_description: |
"address place for rom_system_info"
slave_description: " rom_info "
# reg_system_info
- slave_name : system
slave_type : REG
number_of_fields: 512
- peripheral_name: system_info # pi_system_info.py
peripheral_description: ""
slave_ports:
# MM port for mms_unb2b_board_system_info.vhd / common_rom.vhd
- slave_name: ROM_SYSTEM_INFO # for c_rom_version = 1 in ctrl_unb2b_board.vhd
#- slave_name: ROM_SYSTEM_INFO_V2 # for c_rom_version = 2 in ctrl_unb2b_board.vhd
slave_type: RAM
slave_description: "Memory that stores the MM map system info of the mmap file."
fields:
- - field_name : info
access_mode : RO
- - field_name: ro_data
field_description: "FPGA info memory map data"
access_mode: RO
address_offset: 0x0
number_of_fields: 32
field_description: |
"address place for reg_system_info"
slave_description: " reg_info "
number_of_fields: 8192 # c_rom_addr_w in mms_unb2b_board_system_info
# actual hdl name: unb2b_board_wdi_reg
- slave_name : ctrl
slave_type : REG
# MM port for mms_unb2b_board_system_info.vhd / unb2b_board_system_info_reg.vhd
- slave_name: PIO_SYSTEM_INFO
slave_type: REG
slave_description: "FPGA design name, design note, version and location index info."
fields:
- - field_name : nios_reset
width : 32
access_mode : WO
address_offset : 0x0
number_of_fields: 4
field_description: " Reset done by nios "
slave_description: "Reset register, for nios "
# All registers in one array
#- - field_name: info
# field_description: "FPGA info register, see pi_system_info.py for field details."
# access_mode: RO
# address_offset: 0x0
# number_of_fields: 32
# actual hdl name: unb2b_board_wdi_reg
- slave_name : wdi
slave_type : REG
fields:
- - field_name : reset_word
access_mode : WO
# Each field specified
- "info": # field_group
- field_name: gn_index
field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
width: 8
bit_offset: 0
access_mode: RO
address_offset: 0x0
field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
slave_description: "Reset register, if the right value is provided the factory image will be reloaded "
# actual hdl name: reg_unb2b_sens
- slave_name : board_sens
slave_type : REG
- field_name: hw_version
field_description: "UniBoard2 hardware (HW) version."
width: 2
bit_offset: 8
access_mode: RO
address_offset: 0x0
- field_name: cs_sim
field_description: "0 when running on HW, 1 when running in simulation."
width: 1
bit_offset: 10
access_mode: RO
address_offset: 0x0
- field_name: fw_version_major
field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
width: 4
bit_offset: 16
access_mode: RO
address_offset: 0x0
- field_name: fw_version_minor
field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
width: 4
bit_offset: 20
access_mode: RO
address_offset: 0x0
- field_name: rom_version
field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
width: 3
bit_offset: 24
access_mode: RO
address_offset: 0x0
- field_name: technology
field_description: "FPGA technology"
width: 5
bit_offset: 27
access_mode: RO
address_offset: 0x0
- - field_name: use_phy
field_description: "PHY interfaces that are active in the FPGA, not used."
width: 8
access_mode: RO
address_offset: 0x4
- - field_name: design_name
field_description: "FPGA FW design name string."
access_mode: RO
address_offset: 0x8
number_of_fields: 13
- - field_name: stamp_date
field_description: "FPGA FW compile date string."
access_mode: RO
address_offset: 0x3C
number_of_fields: 1
- - field_name: stamp_time
field_description: "FPGA FW compile time string."
access_mode: RO
address_offset: 0x40
number_of_fields: 1
- - field_name: stamp_commit
field_description: "FPGA FW commit hash string."
access_mode: RO
address_offset: 0x44
number_of_fields: 3
- - field_name: design_note
field_description: "FPGA FW design note string."
access_mode: RO
address_offset: 0x50
number_of_fields: 13
- peripheral_name: wdi # pi_wdi.py
peripheral_description: ""
slave_ports:
# MM port for unb2b_board_wdi_reg.vhd
- slave_name: REG_WDI
slave_type: REG
slave_description: "Reset register, if the right value is provided the factory image will be reloaded in the FPGA."
fields:
- - field_name : sens
width : 32
access_mode : RO
address_offset: 0x00
number_of_fields: 41
field_description: ""
slave_description: " "
- slave_name : board_pmbus
slave_type : REG
fields:
- - field_name : pmbus
width : 32
access_mode : RO
address_offset: 0x00
number_of_fields: 43
field_description: ""
slave_description: " "
- - field_name: wdi_override
field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload."
access_mode: WO
address_offset: 0x0
# actual hdl name: reg_unb2b_sens
- slave_name : fpga_temp
slave_type : REG
- peripheral_name: unb2_fpga_sens
peripheral_description: ""
slave_ports:
# MM ports for mms_unb2b_fpga_sens.vhd / unb2b_fpga_sens_reg.vhd
- slave_name: REG_FPGA_TEMP_SENS # pi_unb_fpga_sens.py
slave_type: REG
slave_description: |
"FPGA temperature = (AxC)/1024 - B (where A=708; B=273; C=adc value), see page 10 in
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alttemp_sense.pdf"
fields:
- - field_name : temp
width : 32
access_mode : RO
address_offset: 0x00
- - field_name: temp
field_description: "Raw data"
access_mode: RO
address_offset: 0x0
number_of_fields: 1
field_description: ""
slave_description: " "
- slave_name : fpga_voltage
slave_type : REG
fields:
- - field_name : voltage
width : 32
access_mode : RO
address_offset: 0x00
number_of_fields: 6
field_description: ""
slave_description: " "
- slave_name : scrap_ram
slave_type : RAM
- slave_name: REG_FPGA_VOLTAGE_SENS # pi_unb_fpga_voltagesens.py
slave_type: REG
slave_description: "Not used, FPGA voltages are monitored via DC-DC converter power supply volages"
fields:
- - field_name: data
width : 32
access_mode: RW
address_offset: 0x00
number_of_fields: 128
field_description: " "
slave_description: " "
peripheral_description: |
""
\ No newline at end of file
- - field_name: voltages
field_description: "Not used"
access_mode: RO
address_offset: 0x0
number_of_fields: 6
libraries/base/diag/diag.peripheral.yaml
+ 94
− 105
View file @ 22e99c4b
schema_name : args
schema_name: args
schema_version: 1.0
schema_type : peripheral
schema_type: peripheral
hdl_library_name : diag
hdl_library_name: diag
hdl_library_description: " This is the description for the bf package "
peripherals:
-
peripheral_name: block_gen
- peripheral_name: block_gen
peripheral_description: "Block generator"
parameters:
- { name: g_nof_streams, value: 1 }
......@@ -16,129 +16,64 @@ peripherals:
slave_ports:
# actual hdl name: reg_diag_bg
- slave_name : ctrl
slave_type : REG
- slave_name: ctrl
slave_description: ""
slave_type: REG
fields:
- - field_name : Enable
width : 2
- - field_name: Enable
field_description: "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
width: 2
address_offset: 0x0
field_description: |
"Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
- - field_name : Samples_per_packet
width : 16
- - field_name: Samples_per_packet
field_description: "This REG specifies the number samples in a packet"
width: 16
address_offset: 0x4
reset_value : 256
field_description: |
"This REG specifies the number samples in a packet"
reset_value: 256
- - field_name : Blocks_per_sync
width : 16
- - field_name: Blocks_per_sync
field_description: "This REG specifies the number of packets in a sync period"
width: 16
address_offset: 0x8
reset_value : 781250
field_description: |
"This REG specifies the number of packets in a sync period"
reset_value: 781250
- - field_name : Gapsize
width : 16
- - field_name: Gapsize
field_description: "This REG specifies the gap in number of clock cycles between two consecutive packets"
width: 16
address_offset: 0xc
reset_value : 80
field_description: |
"This REG specifies the gap in number of clock cycles between two consecutive packets"
reset_value: 80
- - field_name : Mem_low_address
width : 8
- - field_name: Mem_low_address
field_description: "This REG specifies the starting address for reading from the waveform memory"
width: 8
address_offset: 0x10
field_description: |
"This REG specifies the starting address for reading from the waveform memory"
- - field_name : Mem_high_address
width : 8
- - field_name: Mem_high_address
field_description: "This REG specifies the last address to be read when from the waveform memory"
width: 8
address_offset: 0x14
field_description: |
"This REG specifies the last address to be read when from the waveform memory"
- - field_name : BSN_init_low
- - field_name: BSN_init_low
field_description: "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
address_offset: 0x18
field_description: |
"This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
- - field_name : BSN_init_high
- - field_name: BSN_init_high
field_description: "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
address_offset: 0x1c
field_description: |
"This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
slave_description: ""
# actual hdl name: ram_diag_bg
- slave_name : wave_data
- slave_name: wave_data
slave_description: ""
slave_type: RAM
number_of_slaves: g_nof_streams
slave_type : RAM
fields:
- - field_name: diag_bg
width: g_buf_dat_w
number_of_fields: 2**g_buf_addr_w
field_description : |
field_description: |
"Contains the Waveform data for the data-streams to be send"
slave_description: ""
peripheral_description: |
"Block generator"
- peripheral_name: data_buffer
parameters:
- { name: g_nof_streams , value: 1 }
- { name: g_data_w , value: 32 }
- { name: g_buf_nof_data, value: 1024 }
slave_ports:
# actual hdl name: reg_diag_data_buffer
- slave_name : status
slave_type : REG
fields:
- - field_name : Sync_cnt
access_mode : RO
address_offset: 0x0
field_description: |
"Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
(cleared when the last data word from the buffer is read)"
- - field_name : Word_cnt
access_mode : RO
address_offset: 0x4
field_description: |
"Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
- - field_name : Valid_cnt_arm_ena
address_offset: 0x8
field_description: |
"Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
Arm_enable: Write to this REG to arm the system.
After the system is armed the next syn pulse will trigger the acquisition of data."
- - field_name : Reg_sync_delay
address_offset: 0xc
field_description: |
"Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
before the data is written to the databuffer."
- - field_name : Version
access_mode : RO
address_offset: 0x1c
field_description: |
"Version contains the version number of the databuffer peripheral."
slave_description: ""
# actual hdl name: ram_diag_data_buffer
- slave_name : data
number_of_slaves: g_nof_streams
slave_type : RAM
fields:
- - field_name : ram
width : g_data_w
number_of_fields: g_buf_nof_data
field_description: |
"Contains the data that is being captured."
slave_description: ""
peripheral_description: |
"Peripheral diag_data_buffer
......@@ -148,7 +83,7 @@ peripherals:
gets an instanceName as post fix so RAM_DIAG_DATA_BUFFER_<instanceName|.
The diag_data_buffer can store multiple streams in parallel. For example
1024 data words for 16 streams the memory map becomes: 16
1024 data words for 16 streams the memory map becomes: 16
streamNr = 0:
......@@ -162,7 +97,7 @@ peripherals:
+------------------------------------------------------------+
streamNr = 1:
streamNr = 1:
+------------------------------------------------------------+
| byte 3 | byte 2 | byte 1 | byte 0 | wi |
|------------------------------------------------------------|
......@@ -173,7 +108,7 @@ peripherals:
+------------------------------------------------------------+
streamNr = 15:
streamNr = 15:
+------------------------------------------------------------+
| byte 3 | byte 2 | byte 1 | byte 0 | wi |
|------------------------------------------------------------|
......@@ -243,3 +178,57 @@ peripherals:
- reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
before the data is written to the databuffer.
- version contains the version number of the databuffer peripheral."
parameters:
- { name: g_nof_streams , value: 1 }
- { name: g_data_w , value: 32 }
- { name: g_buf_nof_data, value: 1024 }
slave_ports:
# actual hdl name: reg_diag_data_buffer
- slave_name: status
slave_description: ""
slave_type: REG
fields:
- - field_name: Sync_cnt
field_description: |
"Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
(cleared when the last data word from the buffer is read)"
access_mode: RO
address_offset: 0x0
- - field_name: Word_cnt
field_description: |
"Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
access_mode: RO
address_offset: 0x4
- - field_name: Valid_cnt_arm_ena
field_description: |
"Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
Arm_enable: Write to this REG to arm the system.
After the system is armed the next syn pulse will trigger the acquisition of data."
address_offset: 0x8
- - field_name: Reg_sync_delay
field_description: |
"Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
before the data is written to the databuffer."
address_offset: 0xc
- - field_name: Version
field_description: "Version contains the version number of the databuffer peripheral."
access_mode: RO
address_offset: 0x1c
# actual hdl name: ram_diag_data_buffer
- slave_name: data
slave_description: ""
slave_type: RAM
number_of_slaves: g_nof_streams
fields:
- - field_name: ram
width: g_data_w
number_of_fields: g_buf_nof_data
field_description: "Contains the data that is being captured."
libraries/base/dp/dp.peripheral.yaml
+ 51
− 52
View file @ 22e99c4b
schema_name : args
schema_name: args
schema_version: 1.0
schema_type : peripheral
schema_type: peripheral
hdl_library_name : dp
hdl_library_description: " This is the description for the dp package "
hdl_library_name: dp
hdl_library_description: "Data path (DP) peripherals for streaming data."
peripherals:
- peripheral_name: bsn
parameters:
- { name: g_nof_input, value : 2 }
- peripheral_name: dpmm # pi_dpmm.py
peripheral_description: "DP to MM FIFO to provide memory mapped MM read access from Data Path (DP) streaming interface."
slave_ports:
# actual hdl name: reg_dp_bsn_align
- slave_name : ALIGN
number_of_slaves: g_nof_input
slave_type : REG
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm_reg.vhd
- slave_name: REG_DPMM_CTRL
slave_type: REG
slave_description: "DPMM = Monitor the DP to MM read FIFO."
fields:
- - field_name : Enable
width : 1
address_offset : 0x0
field_description: |
"Input enable register for input 0. If set to 0 the input is discarded from alignment.
If set to 1 the corresopnding input is taken into account."
slave_discription: " "
peripheral_description: "This is the BSN aligner"
- peripheral_name: fifo
parameters:
- { name : g_nof_streams, value: 3 }
slave_ports:
# actual hdl name: reg_dp_fifo_fill
- slave_name : fill_status
number_of_slaves: g_nof_streams
slave_type : REG
- - field_name: rd_usedw
field_description: "Number of words that can be read from the FIFO."
access_mode: RO
address_offset: 0x0
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm.vhd
- slave_name: REG_DPMM_DATA # Use REG_, instead of preferred FIFO_, to match slave_port_name in pi_dpmm.py
slave_type: FIFO
slave_description: "DPMM = read word from the DP to MM read FIFO"
fields:
- - field_name : fifo_used_words
access_mode : RO
address_offset : 0x0
field_description: "Register reflects the currently used nof words on the fifo."
- - field_name : fifo_status
width : 2
access_mode : RO
address_offset : 0x4
field_description: "Bit 0: fifo_read_empty Bit 1: fifo_wr_full."
- - field_name : max_fifo_used_words
access_mode : RO
address_offset : 0x8
field_description: |
"Register contains the maximum number of words that have been in the fifo.
Will be cleared after it has been read."
slave_discription: ""
peripheral_description: "This is the MM slave version of the dp_fifo_fill component."
- - field_name: rd_data
field_description: "Read data from the FIFO."
access_mode: RO
address_offset: 0x0
- peripheral_name: mmdp # pi_mmdp.py
peripheral_description: "MM to DP FIFO to provide memory mapped MM write access to Data Path (DP) streaming interface."
slave_ports:
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm_reg.vhd
- slave_name: REG_MMDP_CTRL
slave_type: REG
slave_description: "MMDP = Monitor the MM to DP write FIFO."
fields:
- - field_name: wr_usedw
field_description: "Number of words that are in the write FIFO."
access_mode: RO
address_offset: 0x0
- - field_name: wr_availw
field_description: "Number of words that can be written to the write FIFO."
access_mode: RO
address_offset: 0x4
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm.vhd
- slave_name: REG_MMDP_DATA # Use REG_, instead of preferred FIFO_, to match slave_port_name in pi_mmdp.py
slave_type: FIFO
slave_description: "MMDP = write word to the MM to DP write FIFO"
fields:
- - field_name: data
field_description: "Write data to the FIFO."
access_mode: WO
address_offset: 0x0
libraries/io/epcs/epcs.peripheral.yaml
+ 50
− 104
View file @ 22e99c4b
schema_name : args
schema_name: args
schema_version: 1.0
schema_type : peripheral
schema_type: peripheral
hdl_library_name : epcs
hdl_library_description: " This is the description for the epcs package "
hdl_library_name: epcs
hdl_library_description: "Serial Configuration (EPCS) Device"
peripherals:
# epcs_reg
-
peripheral_name: epcs
- peripheral_name: epcs # pi_epcs.py
peripheral_description: |
"Provide write and read to the flash memory of the FPGA using the EPCS [1]. The write access goes
via a write FIFO (MM to DP) and the read access goes via a read FIFO (DP to MM). The FIFOs
convert between the memory mapped (MM) interface and the data path (DP) streaming interface of
the EPCS [2].
[1] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/epcs/src/vhdl/epcs_reg.vhd
[2] https://git.astron.nl/desp/upe_gear/-/blob/master/peripherals/util_epcs.py"
parameters:
- {name: "g_sim_flash_model", value: TRUE}
# parameters of mms_epcs.vhd / epcs_reg.vhd
- {name: "g_epcs_addr_w", value: 24}
slave_ports:
# actual hdl name: epcs_reg
- slave_name : EPCS
slave_type : REG
# MM port for epcs_reg.vhd
- slave_name: REG_EPCS # pi_epcs.py
slave_type: REG
slave_description: "Handle the read, erase and write of the flash memory chip."
fields:
- - field_name : addr
width : 24
access_mode : WO
- - field_name: addr
field_description: "Address to write to or read from."
width: 24
access_mode: WO
address_offset: 0x0
field_description: " address to write to or read from "
- - field_name : rden
width : 1
access_mode : WO
- - field_name: rden
field_description: "Read enable bit."
width: 1
access_mode: WO
address_offset: 0x4
field_description: " Read enable bit "
- - field_name : read_bit
width : 1
access_mode : WO
side_effect : PW
- - field_name: read_bit
field_description: "Read bit."
width: 1
access_mode: WO
side_effect: PW
address_offset: 0x8
field_description: " Read bit "
- - field_name : write_bit
width : 1
access_mode : WO
side_effect : PW
- - field_name: write_bit
field_description: "Write bit."
width: 1
access_mode: WO
side_effect: PW
address_offset: 0xc
field_description: " Write bit "
- - field_name : sector_erase
width : 1
access_mode : WO
- - field_name: sector_erase
field_description: "Sector erase bit."
width: 1
access_mode: WO
address_offset: 0x10
field_description: " Sector erase bit "
- - field_name : busy
width : 1
access_mode : RO
- - field_name: busy
field_description: "Busy bit."
width: 1
access_mode: RO
address_offset: 0x14
field_description: " busy "
- - field_name : unprotect
width : 32
access_mode : WO
- - field_name: unprotect
field_description: "Use 0xBEDA221E (= Bedazzle) as password to unprotect address range."
width: 32
access_mode: WO
address_offset: 0x18
field_description: " passphrase to unprotect address range "
slave_description: " Read and write access to flash "
# actual hdl name: mms_dp_fifo_to_mm
- slave_name : DPMM_CTRL
slave_type : REG
fields:
- - field_name : ctrl
width : 32
access_mode : RW
address_offset: 0x0
number_of_fields: 1
field_description: " "
slave_description: " "
- slave_name : DPMM_DATA
slave_type : FIFO
fields:
- - field_name : data
width : 32
access_mode : RO
address_offset: 0x0
number_of_fields: 1
field_description: " "
slave_description: " "
# actual hdl name: mms_dp_fifo_from_mm
- slave_name : MMDP_CTRL
slave_type : REG
fields:
- - field_name : ctrl
width : 32
access_mode : RW
address_offset: 0x0
number_of_fields: 2
field_description: " "
slave_description: " "
- slave_name : MMDP_DATA
slave_type : FIFO
fields:
- - field_name : data
width : 32
access_mode : WO
address_offset: 0x0
number_of_fields: 2
field_description: " "
slave_description: " "
peripheral_description: |
"wi Bits SE R/W Name Default Description |REG_EPCS|
=============================================================================
0 [23..0] WO addr 0x0 Address to write to/read from
1 [0] WO rden 0x0 Read enable
2 [0] PW WE read 0x0 Read
3 [0] PW WE write 0x0 Write
4 [0] WO sector_erase 0x0 Sector erase
5 [0] RO busy 0x0 Busy
============================================================================="
\ No newline at end of file
libraries/io/eth/eth.peripheral.yaml
+ 41
− 44
View file @ 22e99c4b
schema_name : args
schema_name: args
schema_version: 1.0
schema_type : peripheral
schema_type: peripheral
hdl_library_name : eth
hdl_library_description: " This is the description for the eth package "
hdl_library_name: eth
hdl_library_description: "Triple Speed Ethernet (TSE) peripheral for 1GbE."
peripherals:
-
peripheral_name: eth1g
parameters:
- { name: c_eth_ram_nof_words, value: 1024 }
#g_technology: c_tech_select_default
#g_ETH_PHY : "LVDS"
- peripheral_name: eth # pi_eth.py
peripheral_description: |
"The ETH module connects the 1GbE TSE [1] to the microprocessor and to streaming UDP ports [2]. The
packets for the streaming channels are directed based on the UDP port number and all other packets
are transfered to the default control channel and handled by the microprocessor.
[1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
[2] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/eth/doc/ASTRON_RP_396_eth_1gb_module.pdf"
slave_ports:
# actual hdl name: reg_tse
- slave_name : TSE
slave_type : REG
# MM port for registers in the TSE IP [1]
- slave_name: AVS_ETH_0_TSE
slave_type: REG
slave_description: "Registers in the TSE IP [1], handled by the microprocessor."
fields:
- - field_name : status
access_mode : RO
address_offset : 0x0
number_of_fields: 1024
field_description: "reg tse"
slave_description: " "
- - field_name: status
field_description: ""
access_mode: RO
address_offset: 0x0
number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
# actual hdl name: reg
- slave_name : ETH
slave_type : REG
# MM port for registers in eth_mm_registers.vhd in the ETH module [2]
- slave_name: AVS_ETH_0_REG
slave_type: REG
slave_description: "Registers in the ETH module [2], handled by the microprocessor."
fields:
- - field_name : status
access_mode : RO
address_offset : 0x0
number_of_fields: 12
field_description: "reg registers"
slave_description: " "
- - field_name: status
field_description: ""
access_mode: RO
address_offset: 0x0
number_of_fields: 12 # = c_eth_reg_nof_words in eth_pkg.vhd
# actual hdl name: ram
- slave_name : ETH
slave_type : RAM
# MM port for ETH packet packet buffers in eth.vhd
- slave_name: AVS_ETH_0_RAM
slave_type: RAM
slave_description: |
"Buffer RAM for request packets (Rx) and response packets (Tx) via 1GbE, used by the microprocessor
to receive and transmit packets via the ETH module."
fields:
- - field_name : ram
number_of_fields: c_eth_ram_nof_words
field_description: |
"Contains the Waveform data for the data-streams to be send"
slave_description: " "
peripheral_description: |
"
Connect the 1GbE TSE to the microprocessor and to streaming UDP ports. The
packets for the streaming channels are directed based on the UDP port
number and all other packets are transfered to the default control channel."
- - field_name: data
field_description: "Data 32b-word."
number_of_fields: 1024 # = c_eth_ram_nof_words in eth_pkg.vhd
libraries/io/ppsh/ppsh.peripheral.yaml
+ 57
− 33
View file @ 22e99c4b
schema_name : args
schema_name: args
schema_version: 1.0
schema_type : peripheral
schema_type: peripheral
hdl_library_name : ppsh
hdl_library_description: " This is the description for the finppshge_stop library "
hdl_library_name: ppsh
hdl_library_description: "Pulse Per Second Handler"
peripherals:
-
peripheral_name: ppsh
- peripheral_name: ppsh # pi_ppsh.py
peripheral_description: |
"Capture PPS input signal and monitor its period. See description in [1, 2] and usage in [3].
[1] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/ppsh/doc/ASTRON_RP_1374_ppsh_module_description.pdf
[2] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
[3] https://git.astron.nl/desp/upe_gear/-/blob/master/peripherals/util_ppsh.py"
parameters:
# parameters of ppsh_reg.vhd
- { name: g_cross_clock_domain, value: TRUE }
- { name: g_st_clk_freq, value: 200 * 10**6 }
slave_ports:
# actual hdl name: reg_ppsh
- slave_name : PPSH
slave_type : REG
# MM port for ppsh_reg.vhd
- slave_name: PIO_PPS # pi_ppsh.py and in QSYS system.h
slave_type: REG
slave_description: "Monitor and control PPS input."
dual_clock: g_cross_clock_domain
fields:
- - field_name : status
access_mode : RO
- - field_name: capture_cnt
field_description: "Measured number of clock cycles between captured PPS pulses."
width: 30
bit_offset: 0
access_mode: RO
address_offset: 0x0
radix: unsigned
- - field_name: stable
field_description: "PPS is stable (1) when capture_cnt = expected_cnt for all PPS periods since last time status was read, else PPS is not stable (0)."
width: 1
bit_offset: 30
access_mode: RO
address_offset: 0x0
- - field_name: toggle
field_description: "Level bit that toggles after every PPS."
width: 1
bit_offset: 31
access_mode: RO
address_offset: 0x0
field_description: " ppsh status "
- - field_name : control
- - field_name: expected_cnt
field_description: "Expected number of clock cycles between captured PPS pulses."
width: ceil_log2(g_st_clk_freq)
bit_offset: 0
access_mode: RW
address_offset: 0x4
radix: unsigned
- - field_name: edge
field_description: "When 0 then clock PPS in on rising edge of clock, else when 1 use falling edge of clock."
width: 1
bit_offset: 31
access_mode: RW
address_offset: 0x4
field_description: " ppsh control "
- - field_name : offset
- - field_name: offset_cnt
field_description: "Number of clock cycles at read access, that has passed since last PPS."
address_offset: 0x8
field_description: " ppsh offset count "
slave_discription: " "
peripheral_description: |
"
. Report PPS toggle, stable and period capture count
. Set dp_clk capture edge for PPS
Set expected period capture count for PPS stable
+----------------------------------------------------------------------------+
|31 (byte3) 24|23 (byte2) 16|15 (byte1) 8|7 (byte0) 0| wi |
|-----------------------------------------------------------------------|----|
|toggle[31], stable[30] xxx capture_cnt = [29:0]| 0 |
|-----------------------------------------------------------------------|----|
|edge[31], xxx expected_cnt = [29:0]| 1 |
|-----------------------------------------------------------------------|----|
| xxx offset_cnt = [29:0]| 2 |
+----------------------------------------------------------------------------+"
width: ceil_log2(g_st_clk_freq)
access_mode: RO
radix: unsigned
libraries/io/remu/remu.peripheral.yaml
+ 46
− 56
View file @ 22e99c4b
schema_name : args
schema_name: args
schema_version: 1.0
schema_type : peripheral
schema_type: peripheral
hdl_library_name : remu
hdl_library_description: " This is the description for the remu package "
hdl_library_name: remu
hdl_library_description: "Remote Update (REMU)"
peripherals:
# peripheral, remu_reg
- peripheral_name: remu
- peripheral_name: remu # pi_remu.py
peripheral_description: |
"Remote update to load the factory image or the user from flash into the the FPGA. See description in [1] and usage in [2].
[1] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/remu/src/vhdl/remu_reg.vhd
[2] https://git.astron.nl/desp/upe_gear/-/blob/master/peripherals/util_remu.py"
parameters:
# parameters of remu_reg.vhd
- { name: g_data_w, value: 24 }
slave_ports:
# actual hdl name: reg_remu
- slave_name : REMU
slave_type : REG
# MM port for remu_reg.vhd
- slave_name: REG_REMU # pi_remu.py and in QSYS system.h
slave_type: REG
slave_description: "Remote update."
fields:
- - field_name : reconfigure_key
width : c_word_w
access_mode : WO
- - field_name: reconfigure
field_description: "Use 0xB007FAC7 (= boot factory) as password to reconfigure."
width: c_word_w
access_mode: WO
address_offset: 0x0
field_description: " reconfigure key for safety "
- - field_name : param
width : 3
access_mode : WO
- - field_name: param
field_description: "param"
width: 3
access_mode: WO
address_offset: 0x4
radix : unsigned
field_description: " "
radix: unsigned
- - field_name : read_param
width : 1
access_mode : WO
side_effect : PW
- - field_name: read_param
field_description: "read_param"
width: 1
access_mode: WO
side_effect: PW
address_offset: 0x8
field_description: " read_param "
- - field_name : write_param
width : 1
access_mode : WO
side_effect : PW
- - field_name: write_param
field_description: "write_param"
width: 1
access_mode: WO
side_effect: PW
address_offset: 0xc
field_description: " write_param "
- - field_name : data_out
width : g_data_w
access_mode : RO
- - field_name: data_out
field_description: "data_out"
width: g_data_w
access_mode: RO
address_offset: 0x10
field_description: " data_out "
- - field_name : data_in
width : g_data_w
access_mode : WO
- - field_name: data_in
field_description: "data_in"
width: g_data_w
access_mode: WO
address_offset: 0x14
field_description: " data_in "
- - field_name : busy
width : 1
access_mode : RO
- - field_name: busy
field_description: "busy"
width: 1
access_mode: RO
address_offset: 0x18
field_description: " busy "
slave_description: " Remote Upgrade "
peripheral_description: |
"wi Bits R/W SE Name Default Description |REG_EPCS|
=============================================================================
0 [31..0] WO reconfigure_key 0x0
1 [2..0] WO param
2 [0] WO PW read_param
3 [0] WO PW write_param
4 [23..0] RO data_out
5 [23..0] WO data_in
6 [0] RO busy
=============================================================================
"
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