Added missing g_tx_crc so sim_tse component, after regression test fail of tb_tb_tech_tse.

libraries/technology/tse/tech_tse.vhd

@@ -84,6 +84,7 @@ ARCHITECTURE str OF tech_tse IS
   COMPONENT sim_tse IS 
   GENERIC(
     g_tx         : BOOLEAN;
+    g_tx_crc     : BOOLEAN := TRUE;  -- model append CRC by TSE MAC, CRC value = 0
     g_rx         : BOOLEAN
   );      
   PORT(
@@ -191,7 +192,7 @@ BEGIN
 
   gen_sim_tse : IF c_use_sim_model=TRUE GENERATE
     u_sim_tse : sim_tse
-    GENERIC MAP (g_sim_tx, g_sim_rx)
+    GENERIC MAP (g_sim_tx, TRUE, g_sim_rx)
     PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
               mm_sla_in, mm_sla_out,
               tx_snk_in, tx_snk_out,