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Commit 20d01ea0 authored by Pepping's avatar Pepping
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- Removed ddr3 lib 

- UPdated for only one memeory controller
parent 76dec372
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boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+ 104
− 124
View file @ 20d01ea0
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib, ddr3_lib; LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
...@@ -32,15 +32,13 @@ USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; ...@@ -32,15 +32,13 @@ USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL; USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL; USE mm_lib.mm_file_unb_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
USE ddr3_lib.ddr3_pkg.ALL;
USE eth_lib.eth_pkg.ALL; USE eth_lib.eth_pkg.ALL;
ENTITY mmm_unb1_ddr3 IS ENTITY mmm_unb1_ddr3 IS
GENERIC ( GENERIC (
g_sim : BOOLEAN := TRUE; --FALSE: use SOPC; TRUE: use mm_file I/O g_sim : BOOLEAN := TRUE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 0
g_nof_MB : NATURAL := 2
); );
PORT ( PORT (
-- GENERAL -- GENERAL
...@@ -59,6 +57,10 @@ ENTITY mmm_unb1_ddr3 IS ...@@ -59,6 +57,10 @@ ENTITY mmm_unb1_ddr3 IS
reg_wdi_mosi : OUT t_mem_mosi; reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso; reg_wdi_miso : IN t_mem_miso;
-- PPSH
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
-- system_info -- system_info
reg_unb_system_info_mosi : OUT t_mem_mosi; reg_unb_system_info_mosi : OUT t_mem_mosi;
reg_unb_system_info_miso : IN t_mem_miso; reg_unb_system_info_miso : IN t_mem_miso;
...@@ -70,12 +72,12 @@ ENTITY mmm_unb1_ddr3 IS ...@@ -70,12 +72,12 @@ ENTITY mmm_unb1_ddr3 IS
reg_unb_sens_miso : IN t_mem_miso; reg_unb_sens_miso : IN t_mem_miso;
-- DDR3 -- DDR3
reg_ddr3_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_MB-1); reg_io_ddr_mosi : OUT t_mem_mosi;
reg_ddr3_miso_arr : IN t_mem_miso_arr(0 TO g_nof_MB-1); reg_io_ddr_miso : IN t_mem_miso;
-- Diagnostics -- Diagnostics
reg_diagnostics_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_MB-1); reg_diagnostics_mosi : OUT t_mem_mosi;
reg_diagnostics_miso_arr : IN t_mem_miso_arr(0 TO g_nof_MB-1); reg_diagnostics_miso : IN t_mem_miso;
-- eth1g -- eth1g
eth1g_tse_clk : OUT STD_LOGIC; eth1g_tse_clk : OUT STD_LOGIC;
...@@ -93,10 +95,8 @@ END mmm_unb1_ddr3; ...@@ -93,10 +95,8 @@ END mmm_unb1_ddr3;
ARCHITECTURE str OF mmm_unb1_ddr3 IS ARCHITECTURE str OF mmm_unb1_ddr3 IS
CONSTANT c_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control intrastructure for two MB's
-- Actual MM address widths, the MM data width is fixed at the default c_word_w=32 -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32
CONSTANT c_mm_reg_ddr3_addr_w : NATURAL := ceil_log2(7); CONSTANT c_mm_reg_io_ddr_addr_w : NATURAL := ceil_log2(16);
CONSTANT c_mm_reg_diagnostics_addr_w : NATURAL := ceil_log2(40); CONSTANT c_mm_reg_diagnostics_addr_w : NATURAL := ceil_log2(40);
-- Simulation -- Simulation
...@@ -177,17 +177,15 @@ BEGIN ...@@ -177,17 +177,15 @@ BEGIN
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS") u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso ); PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ddr3_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDR3_0") u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, i_mm_clk, reg_ddr3_mosi_arr(0), reg_ddr3_miso_arr(0) ); PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_ddr3_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDR3_1") u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
PORT MAP(mm_rst, i_mm_clk, reg_ddr3_mosi_arr(1), reg_ddr3_miso_arr(1) ); PORT MAP(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso );
u_mm_file_reg_dgn_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS_0") u_mm_file_reg_dgn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi_arr(0), reg_diagnostics_miso_arr(0) ); PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_reg_dgn_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS_1")
PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi_arr(1), reg_diagnostics_miso_arr(1) );
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS -- 1GbE setup sequence normally performed by unb_os@NIOS
...@@ -201,10 +199,6 @@ BEGIN ...@@ -201,10 +199,6 @@ BEGIN
WAIT FOR 400 ns; WAIT FOR 400 ns;
WAIT UNTIL rising_edge(i_mm_clk); WAIT UNTIL rising_edge(i_mm_clk);
-- FIXME:
--NEW: proc_tech_tse_setup(g_technology_dut,
--proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX -- Enable RX
proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en
mm_bus_switch <= '0'; mm_bus_switch <= '0';
...@@ -233,7 +227,7 @@ BEGIN ...@@ -233,7 +227,7 @@ BEGIN
-- SOPC for synthesis -- SOPC for synthesis
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
gen_sopc : IF g_sim = FALSE GENERATE gen_sopc : IF g_sim = FALSE GENERATE
u_sopc : ENTITY work.sopc_unb_ddr3 u_sopc : ENTITY work.sopc_unb1_ddr3
PORT MAP ( PORT MAP (
clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
reset_n => xo_rst_n, reset_n => xo_rst_n,
...@@ -280,7 +274,13 @@ BEGIN ...@@ -280,7 +274,13 @@ BEGIN
out_port_from_the_pio_debug_wave => pout_debug_wave, out_port_from_the_pio_debug_wave => pout_debug_wave,
-- the_pio_pps -- the_pio_pps
in_port_to_the_pio_pps => pin_pps, coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_system_info: actually a avs_common_mm instance -- the_pio_system_info: actually a avs_common_mm instance
coe_clk_export_from_the_pio_system_info => OPEN, coe_clk_export_from_the_pio_system_info => OPEN,
...@@ -312,45 +312,25 @@ BEGIN ...@@ -312,45 +312,25 @@ BEGIN
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr, coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0), coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_io_ddr
-- the_reg_ddr3_0 coe_clk_export_from_the_reg_io_ddr => OPEN,
coe_clk_export_from_the_reg_ddr3_0 => OPEN, coe_reset_export_from_the_reg_io_ddr => OPEN,
coe_reset_export_from_the_reg_ddr3_0 => OPEN, coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w-1 DOWNTO 0),
coe_address_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).address(c_mm_reg_ddr3_addr_w-1 DOWNTO 0), coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
coe_read_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).rd, coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
coe_readdata_export_to_the_reg_ddr3_0 => reg_ddr3_miso_arr(0).rddata(c_word_w-1 DOWNTO 0), coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
coe_write_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).wr, coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_writedata_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diagnostics
-- the_reg_diagnostics_0 coe_clk_export_from_the_reg_diagnostics => OPEN,
coe_clk_export_from_the_reg_diagnostics_0 => OPEN, coe_reset_export_from_the_reg_diagnostics => OPEN,
coe_reset_export_from_the_reg_diagnostics_0 => OPEN, coe_address_export_from_the_reg_diagnostics => reg_diagnostics_mosi.address(c_mm_reg_diagnostics_addr_w-1 DOWNTO 0),
coe_address_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).address(c_mm_reg_diagnostics_addr_w-1 DOWNTO 0), coe_read_export_from_the_reg_diagnostics => reg_diagnostics_mosi.rd,
coe_read_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).rd, coe_readdata_export_to_the_reg_diagnostics => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
coe_readdata_export_to_the_reg_diagnostics_0 => reg_diagnostics_miso_arr(0).rddata(c_word_w-1 DOWNTO 0), coe_write_export_from_the_reg_diagnostics => reg_diagnostics_mosi.wr,
coe_write_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).wr, coe_writedata_export_from_the_reg_diagnostics => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0)
coe_writedata_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_ddr3_1
coe_clk_export_from_the_reg_ddr3_1 => OPEN,
coe_reset_export_from_the_reg_ddr3_1 => OPEN,
coe_address_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).address(c_mm_reg_ddr3_addr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).rd,
coe_readdata_export_to_the_reg_ddr3_1 => reg_ddr3_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).wr,
coe_writedata_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diagnostics_1
coe_clk_export_from_the_reg_diagnostics_1 => OPEN,
coe_reset_export_from_the_reg_diagnostics_1 => OPEN,
coe_address_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).address(c_mm_reg_diagnostics_addr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).rd,
coe_readdata_export_to_the_reg_diagnostics_1 => reg_diagnostics_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).wr,
coe_writedata_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0)
); );
END GENERATE; END GENERATE;
END str; END str;
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