diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd index c8a34b1a00760b241d24ce353fe4f9076019cc34..41d1b4b2f19184f42fae280e60c770b733cd3a44 100644 --- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd +++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd @@ -19,7 +19,7 @@ -- ------------------------------------------------------------------------------- -LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib, ddr3_lib; +LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE common_lib.common_pkg.ALL; @@ -32,15 +32,13 @@ USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; USE mm_lib.mm_file_pkg.ALL; USE mm_lib.mm_file_unb_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL; -USE ddr3_lib.ddr3_pkg.ALL; USE eth_lib.eth_pkg.ALL; ENTITY mmm_unb1_ddr3 IS GENERIC ( g_sim : BOOLEAN := TRUE; --FALSE: use SOPC; TRUE: use mm_file I/O g_sim_unb_nr : NATURAL := 0; - g_sim_node_nr : NATURAL := 0; - g_nof_MB : NATURAL := 2 + g_sim_node_nr : NATURAL := 0 ); PORT ( -- GENERAL @@ -58,6 +56,10 @@ ENTITY mmm_unb1_ddr3 IS -- Manual WDI override reg_wdi_mosi : OUT t_mem_mosi; reg_wdi_miso : IN t_mem_miso; + + -- PPSH + reg_ppsh_mosi : OUT t_mem_mosi; + reg_ppsh_miso : IN t_mem_miso; -- system_info reg_unb_system_info_mosi : OUT t_mem_mosi; @@ -70,12 +72,12 @@ ENTITY mmm_unb1_ddr3 IS reg_unb_sens_miso : IN t_mem_miso; -- DDR3 - reg_ddr3_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_MB-1); - reg_ddr3_miso_arr : IN t_mem_miso_arr(0 TO g_nof_MB-1); + reg_io_ddr_mosi : OUT t_mem_mosi; + reg_io_ddr_miso : IN t_mem_miso; -- Diagnostics - reg_diagnostics_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_MB-1); - reg_diagnostics_miso_arr : IN t_mem_miso_arr(0 TO g_nof_MB-1); + reg_diagnostics_mosi : OUT t_mem_mosi; + reg_diagnostics_miso : IN t_mem_miso; -- eth1g eth1g_tse_clk : OUT STD_LOGIC; @@ -93,14 +95,12 @@ END mmm_unb1_ddr3; ARCHITECTURE str OF mmm_unb1_ddr3 IS - CONSTANT c_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control intrastructure for two MB's - -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32 - CONSTANT c_mm_reg_ddr3_addr_w : NATURAL := ceil_log2(7); + CONSTANT c_mm_reg_io_ddr_addr_w : NATURAL := ceil_log2(16); CONSTANT c_mm_reg_diagnostics_addr_w : NATURAL := ceil_log2(40); -- Simulation - CONSTANT c_mm_clk_period : TIME := 8 ns; -- 500 ps; + CONSTANT c_mm_clk_period : TIME := 8 ns; --500 ps; CONSTANT c_tse_clk_period : TIME := 8 ns; CONSTANT c_cal_clk_period : TIME := 25 ns; @@ -175,19 +175,17 @@ BEGIN PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso ); u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS") - PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso ); - - u_mm_file_reg_ddr3_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDR3_0") - PORT MAP(mm_rst, i_mm_clk, reg_ddr3_mosi_arr(0), reg_ddr3_miso_arr(0) ); + PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso ); - u_mm_file_reg_ddr3_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDR3_1") - PORT MAP(mm_rst, i_mm_clk, reg_ddr3_mosi_arr(1), reg_ddr3_miso_arr(1) ); + u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS") + PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso ); + + u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR") + PORT MAP(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso ); - u_mm_file_reg_dgn_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS_0") - PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi_arr(0), reg_diagnostics_miso_arr(0) ); + u_mm_file_reg_dgn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS") + PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso ); - u_mm_file_reg_dgn_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS_1") - PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi_arr(1), reg_diagnostics_miso_arr(1) ); ---------------------------------------------------------------------------- -- 1GbE setup sequence normally performed by unb_os@NIOS @@ -201,10 +199,6 @@ BEGIN WAIT FOR 400 ns; WAIT UNTIL rising_edge(i_mm_clk); - -- FIXME: - --NEW: proc_tech_tse_setup(g_technology_dut, - --proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi); - -- Enable RX proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en mm_bus_switch <= '0'; @@ -233,124 +227,110 @@ BEGIN -- SOPC for synthesis ---------------------------------------------------------------------------- gen_sopc : IF g_sim = FALSE GENERATE - u_sopc : ENTITY work.sopc_unb_ddr3 + u_sopc : ENTITY work.sopc_unb1_ddr3 PORT MAP ( - clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin - reset_n => xo_rst_n, - mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on - cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration - tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit + clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin + reset_n => xo_rst_n, + mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on + cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration + tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit -- the_altpll_0 - areset_to_the_altpll_0 => '0', - locked_from_the_altpll_0 => mm_locked, - phasedone_from_the_altpll_0 => OPEN, + areset_to_the_altpll_0 => '0', + locked_from_the_altpll_0 => mm_locked, + phasedone_from_the_altpll_0 => OPEN, -- the_avs_eth_0 - coe_clk_export_from_the_avs_eth_0 => OPEN, - coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst, - coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0), - coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr, - coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0), - coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd, - coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0), - coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest, - coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0), - coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr, - coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0), - coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd, - coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0), - coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt, - coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0), - coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr, - coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0), - coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd, - coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0), + coe_clk_export_from_the_avs_eth_0 => OPEN, + coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst, + coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0), + coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr, + coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0), + coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd, + coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0), + coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest, + coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0), + coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr, + coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0), + coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd, + coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0), + coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt, + coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0), + coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr, + coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0), + coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd, + coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0), -- the_reg_unb_sens - coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0), - coe_clk_export_from_the_reg_unb_sens => OPEN, - coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd, - coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0), - coe_reset_export_from_the_reg_unb_sens => OPEN, - coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr, - coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0), + coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0), + coe_clk_export_from_the_reg_unb_sens => OPEN, + coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd, + coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0), + coe_reset_export_from_the_reg_unb_sens => OPEN, + coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr, + coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0), -- the_pio_debug_wave - out_port_from_the_pio_debug_wave => pout_debug_wave, + out_port_from_the_pio_debug_wave => pout_debug_wave, -- the_pio_pps - in_port_to_the_pio_pps => pin_pps, + coe_clk_export_from_the_pio_pps => OPEN, + coe_reset_export_from_the_pio_pps => OPEN, + coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0) + coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd, + coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0), + coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr, + coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0), -- the_pio_system_info: actually a avs_common_mm instance - coe_clk_export_from_the_pio_system_info => OPEN, - coe_reset_export_from_the_pio_system_info => OPEN, - coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), - coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd, - coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), - coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr, - coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0), - - -- the_rom_system_info - coe_clk_export_from_the_rom_system_info => OPEN, - coe_reset_export_from_the_rom_system_info => OPEN, - coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), - coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd, - coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), - coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr, - coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0), + coe_clk_export_from_the_pio_system_info => OPEN, + coe_reset_export_from_the_pio_system_info => OPEN, + coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), + coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd, + coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), + coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr, + coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0), + + -- the_rom_system_info + coe_clk_export_from_the_rom_system_info => OPEN, + coe_reset_export_from_the_rom_system_info => OPEN, + coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), + coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd, + coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), + coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr, + coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0), -- the_pio_wdi - out_port_from_the_pio_wdi => pout_wdi, + out_port_from_the_pio_wdi => pout_wdi, -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy). - coe_clk_export_from_the_reg_wdi => OPEN, - coe_reset_export_from_the_reg_wdi => OPEN, - coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0), - coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd, - coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0), - coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr, - coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0), - + coe_clk_export_from_the_reg_wdi => OPEN, + coe_reset_export_from_the_reg_wdi => OPEN, + coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0), + coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd, + coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0), + coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr, + coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0), - -- the_reg_ddr3_0 - coe_clk_export_from_the_reg_ddr3_0 => OPEN, - coe_reset_export_from_the_reg_ddr3_0 => OPEN, - coe_address_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).address(c_mm_reg_ddr3_addr_w-1 DOWNTO 0), - coe_read_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).rd, - coe_readdata_export_to_the_reg_ddr3_0 => reg_ddr3_miso_arr(0).rddata(c_word_w-1 DOWNTO 0), - coe_write_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).wr, - coe_writedata_export_from_the_reg_ddr3_0 => reg_ddr3_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0), + -- the_reg_io_ddr + coe_clk_export_from_the_reg_io_ddr => OPEN, + coe_reset_export_from_the_reg_io_ddr => OPEN, + coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w-1 DOWNTO 0), + coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd, + coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0), + coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr, + coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0), - -- the_reg_diagnostics_0 - coe_clk_export_from_the_reg_diagnostics_0 => OPEN, - coe_reset_export_from_the_reg_diagnostics_0 => OPEN, - coe_address_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).address(c_mm_reg_diagnostics_addr_w-1 DOWNTO 0), - coe_read_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).rd, - coe_readdata_export_to_the_reg_diagnostics_0 => reg_diagnostics_miso_arr(0).rddata(c_word_w-1 DOWNTO 0), - coe_write_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).wr, - coe_writedata_export_from_the_reg_diagnostics_0 => reg_diagnostics_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0), - - -- the_reg_ddr3_1 - coe_clk_export_from_the_reg_ddr3_1 => OPEN, - coe_reset_export_from_the_reg_ddr3_1 => OPEN, - coe_address_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).address(c_mm_reg_ddr3_addr_w-1 DOWNTO 0), - coe_read_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).rd, - coe_readdata_export_to_the_reg_ddr3_1 => reg_ddr3_miso_arr(1).rddata(c_word_w-1 DOWNTO 0), - coe_write_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).wr, - coe_writedata_export_from_the_reg_ddr3_1 => reg_ddr3_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0), - - -- the_reg_diagnostics_1 - coe_clk_export_from_the_reg_diagnostics_1 => OPEN, - coe_reset_export_from_the_reg_diagnostics_1 => OPEN, - coe_address_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).address(c_mm_reg_diagnostics_addr_w-1 DOWNTO 0), - coe_read_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).rd, - coe_readdata_export_to_the_reg_diagnostics_1 => reg_diagnostics_miso_arr(1).rddata(c_word_w-1 DOWNTO 0), - coe_write_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).wr, - coe_writedata_export_from_the_reg_diagnostics_1 => reg_diagnostics_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0) + -- the_reg_diagnostics + coe_clk_export_from_the_reg_diagnostics => OPEN, + coe_reset_export_from_the_reg_diagnostics => OPEN, + coe_address_export_from_the_reg_diagnostics => reg_diagnostics_mosi.address(c_mm_reg_diagnostics_addr_w-1 DOWNTO 0), + coe_read_export_from_the_reg_diagnostics => reg_diagnostics_mosi.rd, + coe_readdata_export_to_the_reg_diagnostics => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0), + coe_write_export_from_the_reg_diagnostics => reg_diagnostics_mosi.wr, + coe_writedata_export_from_the_reg_diagnostics => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0) ); - END GENERATE; - END str; +