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Commit 76dec372 authored by Pepping's avatar Pepping
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- Removed ddr3 library 

- Added mms_io_ddr instance 
- UPdatated diagnostics instances
parent 7d018c02
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boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+ 156
− 255
View file @ 76dec372
......@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, ddr3_lib, diagnostics_lib;
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diagnostics_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
......@@ -27,236 +27,140 @@ USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE ddr3_lib.ddr3_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY node_unb1_ddr3 IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
g_use_MB_I : NATURAL := 1; -- 1: use MB_I 0: do not use
g_use_MB_II : NATURAL := 1; -- 1: use MB_II 0: do not use
g_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
g_mts : NATURAL := 1066;
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
g_st_dat_w : NATURAL := 256 -- Any power of two 8..256
);
PORT (
-- System
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
-- MM registers
reg_ddr3_mosi_arr : IN t_mem_mosi_arr(0 TO g_nof_MB-1);
reg_ddr3_miso_arr : OUT t_mem_miso_arr(0 TO g_nof_MB-1);
ddr_ref_clk : IN STD_LOGIC;
ddr_ref_rst : IN STD_LOGIC;
-- Clock outputs
ddr_out_clk : OUT STD_LOGIC;
ddr_out_rst : OUT STD_LOGIC;
reg_diagnostics_mosi_arr : IN t_mem_mosi_arr(0 TO g_nof_MB-1);
reg_diagnostics_miso_arr : OUT t_mem_miso_arr(0 TO g_nof_MB-1);
-- MM interface
reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : OUT t_mem_miso;
reg_diagnostics_mosi : IN t_mem_mosi;
reg_diagnostics_miso : OUT t_mem_miso;
-- SO-DIMM Memory Bank I = ddr3_I
MB_I_IN : IN t_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
MB_I_IO : INOUT t_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
MB_I_OU : OUT t_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
-- SO-DIMM Memory Bank II
MB_II_IN : IN t_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
MB_II_IO : INOUT t_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
MB_II_OU : OUT t_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0)
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
END node_unb1_ddr3;
ARCHITECTURE str OF node_unb1_ddr3 IS
SIGNAL ctlr_gen_rst : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL ctlr_gen_clk : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
CONSTANT c_data_w : NATURAL := g_st_dat_w;
CONSTANT c_wr_data_w : NATURAL := c_data_w;
CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
CONSTANT c_rd_data_w : NATURAL := c_data_w;
-- DDR3 DP
SIGNAL wr_siso_arr : t_dp_siso_arr(0 TO g_nof_MB-1);
SIGNAL wr_sosi_arr : t_dp_sosi_arr(0 TO g_nof_MB-1);
SIGNAL rd_siso_arr : t_dp_siso_arr(0 TO g_nof_MB-1);
SIGNAL rd_sosi_arr : t_dp_sosi_arr(0 TO g_nof_MB-1);
SIGNAL wr_siso : t_dp_siso;
SIGNAL wr_sosi : t_dp_sosi;
-- OCT control
SIGNAL ser_term_ctrl : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL par_term_ctrl : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL rd_siso : t_dp_siso;
SIGNAL rd_sosi : t_dp_sosi;
-- ctrl & status Diagnostics
SIGNAL src_diag_en : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL src_diag_md : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL src_val_cnt : t_slv_32_arr(0 TO g_nof_MB-1);
SIGNAL src_val_cnt_clr : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL src_diag_en : STD_LOGIC;
SIGNAL src_diag_md : STD_LOGIC;
SIGNAL src_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL src_val_cnt_clr : STD_LOGIC;
SIGNAL snk_diag_en : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL snk_diag_md : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL snk_diag_en : STD_LOGIC;
SIGNAL snk_diag_md : STD_LOGIC;
SIGNAL snk_diag_res : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL snk_diag_res_val : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL snk_val_cnt : t_slv_32_arr(0 TO g_nof_MB-1);
SIGNAL snk_val_cnt_clr : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
SIGNAL snk_diag_res : STD_LOGIC;
SIGNAL snk_diag_res_val : STD_LOGIC;
SIGNAL snk_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL snk_val_cnt_clr : STD_LOGIC;
BEGIN
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
no_MB_I : IF g_use_MB_I = 0 GENERATE
reg_ddr3_miso_arr(0) <= c_mem_miso_rst;
reg_diagnostics_miso_arr(0) <= c_mem_miso_rst;
END GENERATE;
gen_MB_I : IF g_use_MB_I = 1 GENERATE
u_mms_ddr3: ENTITY ddr3_lib.mms_ddr3
u_mms_ddr3 : ENTITY io_ddr_lib.mms_io_ddr
GENERIC MAP(
g_sim => g_sim,
g_ddr => g_ddr,
g_mts => g_mts,
g_phy => 1,
g_wr_data_w => g_st_dat_w,
g_rd_data_w => g_st_dat_w
g_technology => g_technology, --: NATURAL := c_tech_select_default;
g_tech_ddr => g_tech_ddr, --: t_c_tech_ddr;
g_cross_domain_dvr_ctlr => FALSE, --: BOOLEAN := TRUE;
g_wr_data_w => c_wr_data_w,
g_wr_fifo_depth => c_wr_fifo_depth,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_rd_data_w,
g_wr_flush_mode => "VAL",
g_wr_flush_use_channel => FALSE,
g_wr_flush_start_channel => 0,
g_wr_flush_nof_channels => 1
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
ctlr_ref_clk => dp_clk,
ctlr_rst => dp_rst,
ctlr_gen_clk => ctlr_gen_clk(0),
ctlr_gen_rst => ctlr_gen_rst(0),
wr_clk => dp_clk,
wr_rst => dp_rst,
-- DDR reference clock
ctlr_ref_clk => ddr_ref_clk,
ctlr_ref_rst => ddr_ref_rst,
wr_sosi => wr_sosi_arr(0),
wr_siso => wr_siso_arr(0),
-- DDR controller clock domain
ctlr_clk_out => ddr_out_clk,
ctlr_rst_out => ddr_out_rst,
rd_sosi => rd_sosi_arr(0),
rd_siso => rd_siso_arr(0),
rd_clk => dp_clk,
rd_rst => dp_rst,
ctrl_mosi => reg_ddr3_mosi_arr(0),
ctrl_miso => reg_ddr3_miso_arr(0),
ser_term_ctrl_out => ser_term_ctrl,
par_term_ctrl_out => par_term_ctrl,
ddr3_in => MB_I_in(0),
ddr3_io => MB_I_io(0),
ddr3_ou => MB_I_ou(0)
);
u_diagnostics: ENTITY diagnostics_lib.diagnostics
GENERIC MAP (
g_dat_w => g_st_dat_w
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
ctlr_clk_in => dp_clk,
ctlr_rst_in => dp_rst,
snk_out_arr(0) => rd_siso_arr(0),
snk_in_arr(0) => rd_sosi_arr(0),
snk_diag_en(0) => snk_diag_en(0),
snk_diag_md(0) => snk_diag_md(0),
snk_diag_res(0) => snk_diag_res(0),
snk_diag_res_val(0) => snk_diag_res_val(0),
snk_val_cnt(0) => snk_val_cnt(0),
snk_val_cnt_clr(0) => snk_val_cnt_clr(0),
src_out_arr(0) => wr_sosi_arr(0),
src_in_arr(0) => wr_siso_arr(0),
src_diag_en(0) => src_diag_en(0),
src_diag_md(0) => src_diag_md(0),
src_val_cnt(0) => src_val_cnt(0),
src_val_cnt_clr(0) => src_val_cnt_clr(0)
);
u_diagnostics_reg: ENTITY diagnostics_lib.diagnostics_reg
GENERIC MAP(
g_nof_streams => 1
)
PORT MAP (
-- MM clock + reset
mm_rst => mm_rst,
mm_clk => mm_clk,
st_rst => dp_rst,
st_clk => dp_clk,
sla_in => reg_diagnostics_mosi_arr(0),
sla_out => reg_diagnostics_miso_arr(0),
st_src_en(0) => src_diag_en(0),
st_src_md(0) => src_diag_md(0),
st_src_cnt(0) => src_val_cnt(0),
st_src_cnt_clr_evt(0) => src_val_cnt_clr(0),
st_snk_en(0) => snk_diag_en(0),
st_snk_md(0) => snk_diag_md(0),
st_snk_cnt(0) => snk_val_cnt(0),
st_snk_cnt_clr_evt(0) => snk_val_cnt_clr(0),
st_snk_diag_val(0) => snk_diag_res_val(0),
st_snk_diag_res(0) => snk_diag_res(0)
);
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
END GENERATE;
------------------------------------------------------------------------------
-- DDR3 MODULE 1, MB_II
------------------------------------------------------------------------------
no_MB_II : IF g_use_MB_II = 0 GENERATE
reg_ddr3_miso_arr(1) <= c_mem_miso_rst;
reg_diagnostics_miso_arr(1) <= c_mem_miso_rst;
END GENERATE;
gen_MB_II : IF g_use_MB_II = 1 GENERATE
u_mms_ddr3: ENTITY ddr3_lib.mms_ddr3
GENERIC MAP(
g_sim => g_sim,
g_ddr => g_ddr,
g_mts => g_mts,
g_phy => 2,
g_wr_data_w => g_st_dat_w,
g_rd_data_w => g_st_dat_w
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
ctlr_ref_clk => dp_clk,
ctlr_rst => dp_rst,
ctlr_gen_clk => ctlr_gen_clk(1),
ctlr_gen_rst => ctlr_gen_rst(1),
dvr_clk => dp_clk,
dvr_rst => dp_rst,
-- Write FIFO clock domain
wr_clk => dp_clk,
wr_rst => dp_rst,
wr_sosi => wr_sosi_arr(1),
wr_siso => wr_siso_arr(1),
rd_sosi => rd_sosi_arr(1),
rd_siso => rd_siso_arr(1),
wr_fifo_usedw => OPEN,
wr_sosi => wr_sosi,
wr_siso => wr_siso,
-- Read FIFO clock domain
rd_clk => dp_clk,
rd_rst => dp_rst,
ctrl_mosi => reg_ddr3_mosi_arr(1),
ctrl_miso => reg_ddr3_miso_arr(1),
rd_fifo_usedw => OPEN,
rd_sosi => rd_sosi,
rd_siso => rd_siso,
ser_term_ctrl_in => ser_term_ctrl,
par_term_ctrl_in => par_term_ctrl,
term_ctrl_out => OPEN,
term_ctrl_in => OPEN,
ddr3_in => MB_II_in(0),
ddr3_io => MB_II_io(0),
ddr3_ou => MB_II_ou(0)
-- DDR3 PHY external interface
phy3_in => MB_I_in,
phy3_io => MB_I_io,
phy3_ou => MB_I_ou
);
u_diagnostics: ENTITY diagnostics_lib.diagnostics
......@@ -267,21 +171,21 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
snk_out_arr(0) => rd_siso_arr(1),
snk_in_arr(0) => rd_sosi_arr(1),
snk_diag_en(0) => snk_diag_en(1),
snk_diag_md(0) => snk_diag_md(1),
snk_diag_res(0) => snk_diag_res(1),
snk_diag_res_val(0) => snk_diag_res_val(1),
snk_val_cnt(0) => snk_val_cnt(1),
snk_val_cnt_clr(0) => snk_val_cnt_clr(1),
src_out_arr(0) => wr_sosi_arr(1),
src_in_arr(0) => wr_siso_arr(1),
src_diag_en(0) => src_diag_en(1),
src_diag_md(0) => src_diag_md(1),
src_val_cnt(0) => src_val_cnt(1),
src_val_cnt_clr(0) => src_val_cnt_clr(1)
snk_out_arr(0) => rd_siso,
snk_in_arr(0) => rd_sosi,
snk_diag_en(0) => snk_diag_en,
snk_diag_md(0) => snk_diag_md,
snk_diag_res(0) => snk_diag_res,
snk_diag_res_val(0) => snk_diag_res_val,
snk_val_cnt(0) => snk_val_cnt,
snk_val_cnt_clr(0) => snk_val_cnt_clr,
src_out_arr(0) => wr_sosi,
src_in_arr(0) => wr_siso,
src_diag_en(0) => src_diag_en,
src_diag_md(0) => src_diag_md,
src_val_cnt(0) => src_val_cnt,
src_val_cnt_clr(0) => src_val_cnt_clr
);
u_diagnostics_reg: ENTITY diagnostics_lib.diagnostics_reg
......@@ -294,24 +198,21 @@ BEGIN
st_rst => dp_rst,
st_clk => dp_clk,
sla_in => reg_diagnostics_mosi_arr(1),
sla_out => reg_diagnostics_miso_arr(1),
sla_in => reg_diagnostics_mosi,
sla_out => reg_diagnostics_miso,
st_src_en(0) => src_diag_en(1),
st_src_md(0) => src_diag_md(1),
st_src_cnt(0) => src_val_cnt(1),
st_src_cnt_clr_evt(0) => src_val_cnt_clr(1),
st_src_en(0) => src_diag_en,
st_src_md(0) => src_diag_md,
st_src_cnt(0) => src_val_cnt,
st_src_cnt_clr_evt(0) => src_val_cnt_clr,
st_snk_en(0) => snk_diag_en(1),
st_snk_md(0) => snk_diag_md(1),
st_snk_cnt(0) => snk_val_cnt(1),
st_snk_cnt_clr_evt(0) => snk_val_cnt_clr(1),
st_snk_diag_val(0) => snk_diag_res_val(1),
st_snk_diag_res(0) => snk_diag_res(1)
st_snk_en(0) => snk_diag_en,
st_snk_md(0) => snk_diag_md,
st_snk_cnt(0) => snk_val_cnt,
st_snk_cnt_clr_evt(0) => snk_val_cnt_clr,
st_snk_diag_val(0) => snk_diag_res_val,
st_snk_diag_res(0) => snk_diag_res
);
END GENERATE;
END str;
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