add _e3sge3 option (for unb2a) to technology wrapper

libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd

@@ -61,4 +61,18 @@ BEGIN
     );
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_fractional_pll_clk125
+    PORT MAP (
+  		outclk0       => c0,            --       outclk0.clk
+  		outclk1       => c1,            --       outclk1.clk
+  		outclk2       => c2,            --       outclk2.clk
+  		outclk3       => c3,            --       outclk3.clk
+  		pll_cal_busy  => OPEN,          --  pll_cal_busy.pll_cal_busy
+  		pll_locked    => locked,        --    pll_locked.pll_locked
+  		pll_powerdown => areset,        -- pll_powerdown.pll_powerdown
+  		pll_refclk0   => inclk0         --   pll_refclk0.clk
+    );
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd

@@ -59,4 +59,18 @@ BEGIN
     );
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_fractional_pll_clk200
+    PORT MAP (
+  		outclk0       => c0,            --       outclk0.clk
+  		outclk1       => c1,            --       outclk1.clk
+  		outclk2       => c2,            --       outclk2.clk
+  		pll_cal_busy  => OPEN,          --  pll_cal_busy.pll_cal_busy
+  		pll_locked    => locked,        --    pll_locked.pll_locked
+  		pll_powerdown => areset,        -- pll_powerdown.pll_powerdown
+  		pll_refclk0   => inclk0         --   pll_refclk0.clk
+    );
+  END GENERATE;
+
+END ARCHITECTURE;
 END ARCHITECTURE;