From 1f9d9549ec6d537d854a6e25a9c862b206cefd3e Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Tue, 19 Jan 2016 14:58:39 +0000
Subject: [PATCH] add _e3sge3 option (for unb2a) to technology wrapper
---
.../technology/pll/tech_pll_xgmii_mac_clocks.vhd | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 585a682ec6..a3748668a1 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -79,6 +79,18 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+ u0 : ip_arria10_e3sge3_pll_xgmii_mac_clocks
+ PORT MAP (
+ pll_refclk0 => refclk_644,
+ pll_powerdown => rst_in,
+ pll_locked => pll_locked,
+ outclk0 => i_clk_156,
+ pll_cal_busy => OPEN,
+ outclk1 => i_clk_312
+ );
+ END GENERATE;
+
pll_locked_n <= NOT pll_locked;
-- The delta-cycle difference in simulation between i_clk and output clk is no issue because i_clk is only used to create rst which is not clk cycle critical
--
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